GSI Technology GS82582T37GE-450I

GS82582T19/37GE complies with the SigmaDDR-II+ SRAM pin standard for general-purpose I/O synchronous SRAM. They are 301,989,888-bit (288Mb) SRAMs. The GS82582T19/37GE SigmaDDR-II+ SRAMs are part of a low-power, low-voltage HSTL I/O SRAM family, designed to operate at the speeds required for cost-effective, high-performance networking systems.

• 2.0 clock latency
• Synchronous read/write SigmaDDR interface
• General-purpose I/O bus
• JEDEC standard pinout and packaging
• Double data rate interface
• Byte write control sampled at data input
• Burst length of 2 read/write operations
• On-die termination (ODT) on data (D), byte write (BW), and clock (K, K) inputs
• 1.8V ±100 mV core supply voltage
• 1.5V or 1.8V HSTL interface
• Pipelined read operation with self-timed delayed write
• Fully coherent read/write pipeline
• ZQ pin for programmable output drive strength
• Data valid pin (QVLD) support
• IEEE 1149.1 JTAG-compliant boundary scan
• RoHS-compliant 165-bump BGA package

• Read-dominated applications
• Block transfer applications