MICROCHIP PIC32CX1025MTG128T-I/X9B

The Microchip PIC32CXMTG series is a family of system-on-chip solutions well suited for smart energy applications such as communication modules and residential split meter systems. Built around a 32-bit Arm Cortex-M4F RISC processor, the devices run at a maximum speed of 200 MHz and embed up to 2 Mbytes of embedded Flash, up to 512 Kbytes of SRAM and 16 Kb of Instruction and 8 Kb of Data Cache/Tightly Coupled Memory (TCM) on-chip. A QSPI interface with eXecute-in-Place (XiP) coupled with on-the-fly AES128 encryption bridge futureproofs the devices and ensures platform scalability in case of memory extension needs or changing system requirements. A Secure Boot and secure key storage coupled with advanced cryptographic/Hash hardware accelerators, such as ECC, RSA, AES128/256 and SHA256/512, support the different encryption and authentication protocols. The series also features a segmented LCD controller, anti-tampers, Floating Point Unit (FPU), Memory Protection Unit (MPU), FLEXCOM peripherals supporting I2C, SPI, UART/USART interfaces, three PWMs for pulse output functions, 12-channel general-purpose 32-bit timers, 12-bit ADC, analog comparators and a battery backed-up RTC running as low as 1 μA. PIC32CXMTG devices are available in EP-TQFP128-pin exposed pin and VQFN64 packages.

• Core
  • Arm Cortex-M4F running at up to 200 MHz
  • 16 Kbytes ITCM/I-Cache, 8 Kbytes DTCM/D-Cache
  • Memory Protection Unit (MPU)
  • IEEE 754-compliant, single-precision Floating Point Unit (FPU), DSP instruction, Thumb-2 instruction set
  • Up to 2 Mbytes of embedded dual plane/dual boot Flash
  • Built-in ECC, Read-While-Write (RWW) support and Suspend/Resume of write/erase operations
  • Endurance of 100K Write/Erase cycles (1M in qualification)
• Security and Cryptography
  • Secure Boot
  • Secure key storage and transfer to Advanced Encryption Standard (AES) and AES Bridge (AESB) without processor intervention
  • One-time programmable block for software monotonic counter
  • Security bit to disable debug port access
  • True Random Number Generator (TRNG)
  • Deterministic Random Number Generator (DRNG) support as required by NIST 800-90B
  • AES: 256-, 192-, 128-bit key algorithm, compliant with FIPS PUB-197 specifications, ARIA
  • AES128 on-the-fly encryption/decryption bridge for QSPI communications
  • Secure Hash Algorithm (SHA) supporting SHA1, SHA224, SHA256, SHA384 and SHA512, compliant with FIPS PUB-197 specifications, and associated HMAC
  • Classical Public Key Cryptographic Controller (CPKCC) supporting: RSA up to 7168 bits, elliptic curve, DSA, DRNG
  • 768 bits of General Purpose Backup registers (GPBR) can be defined as write-once
  • Automatic and immediate keys erasing upon detection of Flash erase signal assertion
  • Erase of AES keys, QSPI scrambling keys and GPBR
  • Anti-tamper with time-stamping, configurable and immediate actions upon detection
  • Erase of AES, AESB keys, QSPI scrambling keys and General Purpose Backup registers
  • Integrity Check Module (ICM) based on SHA256, autonomous
• System Controller
  • Power supply
    • Embedded core and LCD voltage regulator for single-supply operation
    • Supply monitors
    • Ultra-low-power Backup mode
• Clock
  • Programmable PLLs and oscillator clock sources
  • Clock failure detection
  • CPU frequency monitor
  • Main crystal oscillator failure detection
  • 32.768 kHz crystal oscillator frequency monitor and failure detection
  • Independent Dual Watchdog Timer (DWDT)
  • 12 MHz internal RC oscillator
  • Ultra-low-power Real-Time Clock (RTC) with Gregorian, Persian calendars and UTC mode, calibration circuitry to compensate the 32.768 kHz crystal drift with observability of compensated clock on output pin
  • Peripheral and memory-to-memory DMA channels
• Shared Peripherals
  • Segmented LCD Controller (SLCDC)
    • Static, ½, % and % bias
    • Software-selectable LCD output voltage (contrast)
    • Can be used in Backup mode
• Communication Interfaces
  • FLEXCOMs supporting U(S)ART, SPI, TWI/I2C with FIFOs
  • Metrology-specific multi-channel SPI with legacy support
  • Metrology-specific two-wire UARTs supporting optical transceiver providing an electrically-isolated serial communication with hand-held equipment, such as calibrators, compliant with ANSI-C12.18 or IEC62056-21 norms
• Debugger Development Support
  • Arm CoreSight JTAG-DP or SW-DP debug port
  • Wake-up from debug request
  • Unlimited software breakpoints
  • IEEE 1149.2-compatible (JTAG) boundary scan
• Analog Conversion Block
  • 12-bit ADC module
    • 1 Msps S/H ADC
    • Up to 8 channels
  • Two analog comparators
  • Temperature sensor
  • Closed-Circuit Voltage (CCV) measurement on battery voltage input rail (VBAT)
• Timers/Output Compare/Input Capture
  • 12-channel 32-bit Timer Counters (TC) with Capture, Waveform, Compare and basic PWM modes. Quadrature decoder logic and 2-bit Gray up/down counter
  • 3-channel, 24-bit PWM with complementary outputs, dead-time generator and external trigger modes
• I/O
  • I/O lines with slew rate control to ease PCB design and EMC compliance, external interrupt capability (edge or level sensitivity), Schmitt trigger, internal pull-up/pull-down, debouncing, glitch filtering and on-die series resistor termination
• Software and Tools Support
  • Microchip Smart Energy Framework Software Examples
  • Microchip G3/PRIME/IEEE PLC Stacks
  • Microchip MPLAB-X & Harmony
  • IAR Embedded WorkBench, Keil μVision
• Packages
  • 64-lead VQFN, 7.5×7.5×0.9 mm, pitch 0.4 mm
  • 128-pin EP-TQFP, 14×14×1.0 mm, pitch 0.4 mm