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Infineon S25HL01GTFAMHV010

Hersteller
Infineon
Herst.-Teilenr.
S25HL01GTFAMHV010
LCSC-Nr.
C5904908
Verp.
SOIC-16-300mil
Kundennummer
Hauptmerkm.
1Gbit 2.7V~3.6V SPI SOIC-16-300mil Memory
DatenblattInfineon S25HL01GTFAMHV010
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Minimum: 1Vielfaches: 1Verkaufseinheit: Piece
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Stk.E-Preis(Nur als Referenz)Gesamtbetrag
1+$ 33.4139$ 33.41
200+$ 13.3332$ 2666.64
500+$ 12.8877$ 6443.85
1,000+$ 12.6664$ 12666.40
Standardgehäuse2400/Full Tray
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Produktspezifikationen

Alle
TypBeschreibung
KategorieIntegrated Circuits (ICs)/Memory/Memory
HerstellerInfineon
Verp.SOIC-16-300mil
Operating Temperature-40℃~+105℃
FeaturesECC error correction;Power-on reset;Hardware write protection;Absolute write protection
Memory Size1Gbit
Voltage - Supply2.7V~3.6V
InterfaceSPI
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KI-Übersetzung
  • 45nm MirrorBit technology, 2 bits per memory array cell
  • Page mode: address space organized in 256KB pages
  • High configuration 2: address space divided equally into 32 × 4KB sectors (top and bottom) and remaining 256KB sectors
  • 256 or 512-byte page program buffer
  • 1024-byte (32×32 bytes) OTP secure silicon array
  • Quad SPI support: 1S-1S-4S, 1S-4S-4S, 1S-4D-4D, 4S-4S-4S, 4S-4D-4D protocols; up to 83Mbps in SDR mode (166MHz clock), up to 102Mbps in DDR mode (102MHz clock)
  • Dual SPI support: 1S-2S-2S protocol; up to 41.5Mbps in SDR mode (166MHz clock)
  • SPI support: 1S-1S-1S protocol; up to 21Mbps in SDR mode (166MHz clock)
  • Industry-first NOR flash safety features compliant with ISO 26262 ASIL B and supporting ASIL D
  • EnduranceFlex architecture: high endurance and long-term data retention
  • Row integrity CRC: error detection in memory array
  • Data path: reports device initialization failures, detects configuration corruption and provides recovery prediction
  • Built-in ECC: single-bit error correction and double-bit error detection (SECDED) for memory array data
  • Erase status indicator: signals power loss during erase operation
  • Register block protection configuration for memory array and device configuration
  • Advanced sector protection at individual memory array sector level
  • Immediate memory array access after power-up
  • Hardware reset via CS# glitch method (JEDEC) / dedicated RESET# pin / DQ3_RESET# pin
  • SFDP output describing device capabilities and features, including Device ID, Manufacturer ID, and Unique ID
  • 256Mb device: minimum 640,000 program/erase cycles for memory array
  • 512Mb device: minimum 1,280,000 program/erase cycles for memory array
  • 1Gb device: minimum 2,560,000 program/erase cycles for main array
  • All devices: minimum 300,000 program/erase cycles for 4KB sectors; minimum 25-year data retention
  • Supply voltage: 1.7V ~ 2.0V (HS-T), 2.7V ~ 3.6V (HS-T)
  • Operating temperature range: Industrial (-40°C ~ +85°C), Industrial Flash (-40°C ~ +105°C), Automotive AEC-Q100 Grade 3 (-40°C ~ +85°C), Automotive AEC-Q100 Grade 2 (-40°C ~ +105°C), Automotive AEC-Q100 Grade 1 (-40°C ~ +125°C)
  • 256MB and 512MB packages: 16-pin SOIC (300mil) - SO3016, 24-ball BGA 6×8mm, 16-pin SOIC (300mil), 8-contact WSON 6×8mm
  • 1GB packages: 16-pin SOIC (300mil) - SO3016, 24-ball BGA 8×8mm, 16-pin SOIC (300mil)