GSI Technology GS81314LD36GK-133I

SigmaQuad-IVe ECCRAM is the independent I/O half of the high-performance ECCRAM family SigmaQuad-IVe/SigmaDDR-IVe. Although similar to GSI's third-generation network SRAM (SigmaQuad-IIIe/SigmaDDR-IIIe series), these fourth-generation devices offer several new features that help significantly improve performance. GSI's ECCRAM implements an ECC algorithm capable of detecting and correcting all single-bit memory errors, including those caused by SER events such as cosmic rays and alpha particles. The soft error rate of these devices is expected to be less than 0.002 FITs/Mb — an improvement of 5 orders of magnitude over comparable SRAMs without on-chip ECC, which typically exhibit an SER of 200 FITs/Mb or higher.

• Available in 4Mb x 36 and 8Mb x 18 organizations
• Organized as 8 logical banks
• Maximum operating frequency: 1333 MHz
• Peak transaction rate: 1.333 BT/s (billion transactions per second)
• Peak data bandwidth: 192 Gb/s (in x36 devices)
• Separate I/O DDR data bus
• Non-multiplexed SDR address bus
• One operation per clock cycle — read or write
• Address/bank restrictions specific to read and write operations
• Burst of 4 read and write operations
• 6-cycle read latency
• On-chip ECC with near-zero soft error rate
• Loopback signal timing training capability
• Nominal core voltage: 1.25V ~ 1.3V
• HSTL I/O interface voltage: 1.2V ~ 1.3V
• Configuration registers
• Configurable on-chip termination
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• Boundary scan compliant with IEEE 1149.1 JTAG standard
• 260-pin, 14mm × 22mm, 1mm ball pitch, 6/6 RoHS-compliant BGA package