TI SNJ54LS379J

These monolithic, positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic with an enable input. The 'LS377, 'LS378, and 'LS379 devices are similar to 'LS273, 'LS174, and 'LS175, respectively, but feature a common enable instead of a common clear.

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input overline{G} is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at theoverline{G} input.

These flip-flops are guaranteed to respond to clock frequencies ranging from 0 to 30 MHz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 10 milliwatts per flip-flop.

• LS377 contains 8 flip-flops; LS378 contains 6 flip-flops; both with single-rail outputs
• LS379 contains 4 flip-flops with complementary (dual-rail) outputs
• Individual data input per flip-flop
• Clock frequency range: 0~30MHz; typical maximum clock frequency: 40MHz
• Typical power dissipation: 10mW per flip-flop
• LS379 data input equivalent resistance: 30kΩ (nominal); all other variants: 25kΩ (nominal)
• LS379 clock input equivalent resistance: 17kΩ (nominal); all other variants: 20kΩ (nominal)
• LS379 enable input equivalent resistance: 25kΩ (nominal); all other variants: 20kΩ (nominal)
• VCC maximum: 7V; input voltage maximum: 7V
• SN54LS series operating free-air temperature range: -55℃~125℃
• Available in J, DW, N, FK, W and other package types; some pins are no internal connection

• Buffer/Storage Registers
• Shift Registers
• Pattern Generators