SKYWORKS SI5344H-D11161-GMR

This dedicated jitter-attenuating clock multiplier combines 4th-generation DSPLL technology with ultra-low phase jitter and MultiSynth technology, enabling high-speed data rate coherent optical transceiver designs. Up to four outputs can be allocated to high-frequency mode, with typical phase jitter as low as 50 fs-rms and maximum frequency up to 2.75 GHz. When additional frequency flexibility is required — such as providing clocking for forward error correction — each output can also be configured for any-frequency output in multi-frequency synthesis mode, while still delivering typical phase jitter below 150 fs-rms. The device also features a digitally controlled oscillator function with step control resolution as fine as 0.001 ppb, and supports locking to clock inputs with gaps. These devices are programmable via a serial interface and feature on-chip programmable non-volatile memory, ensuring power-up in a known frequency configuration at all times. The loop filter is fully integrated on-chip, eliminating the risk of noise coupling that may exist in discrete solutions.

• High-speed outputs generate ultra-low jitter clock signals up to 2.75 GHz
• Up to four multi-frequency synthesis outputs generate arbitrary frequencies up to 717.5 MHz
• Input frequency range: 8 kHz to 750 MHz
• High-frequency mode maximum output frequency: 2.75 GHz
• Multi-frequency synthesis mode maximum output frequency: 717.5 MHz
• High-frequency mode typical jitter performance: <50 fs
• Multi-frequency synthesis mode typical jitter performance: <150 fs
• Programmable jitter attenuation bandwidth: 10 Hz to 4 kHz
• Highly configurable outputs compatible with LVDS, LVPECL, LVMOS, CML, and HCSL standards with programmable voltage swing and common-mode voltage
• High-frequency mode supports LVPECL only
• Status monitoring
• Hitless input clock switching: automatic or manual
• Automatic free-run and holdover modes
• Dynamic glitch-free output frequency change
• Lockable bandgap clock input
• DCO mode: step resolution as fine as 0.001 ppb
• Core supply VDD: 1.8 V ±5%
• Analog supply VDDA: 3.3 V ±5%
• Independent output supply pins: 3.3 V, 2.5 V, or 1.8 V
• Serial interface: I²C or SPI
• In-system programming via non-volatile OTP memory
• Configuration software simplifies device setup
• Operating temperature range: -40 to +85 °C
• Lead-free and RoHS-6 compliant

• 100G/200G/400G optical transceivers
• Hitless input clock switching
• Automatic free-run and holdover modes
• Dynamic glitch-free output frequency change
• Clock input with lock band gap
• Digitally controlled oscillator mode