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SKYWORKS M68R

Produttore
Cod. Prod.
M68R
Cod. LCSC
C3611957
Imballo
LGA-84(29.2x29.2)
Numero Cliente
Attr. chiave
LGA-84(29.2x29.2) Clock Generators, PLLs, Frequency Synthesizers
Scheda TecnicaSKYWORKS M68R
Esaurito
Avvisami
Minimo: 1Multiplo: 1Unità di vendita: Piece
Aggiungi alla Lista BOM
QtàPr. unit.(Solo per riferimento)Importo totale
1+$ 84.3529$ 84.35
30+$ 80.1922$ 2405.77
Package Standard1280/Full Box
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Specifiche del Prodotto

Tutto
TipoDescrizione
CategoriaIntegrated Circuits (ICs)/Clock/Timing/Clock Generators, PLLs, Frequency Synthesizers
ProduttoreSKYWORKS
ImballoLGA-84(29.2x29.2)
FeaturesNetwork synchronizer clock;External oscillator interface

Descrizione

Traduzione AI

This document describes the M68/M64, a family of network synchronization modules for packet network timing applications based on Silicon Labs AccuTime™ technology. In addition to a local oscillator, these modules can use multiple reference time and frequency sources to generate precise time and frequency, including pulse-per-second (PPS) and time-of-day (ToD), as well as time compliant with IEEE Std 1588-2008. IEEE Std 1588-2008 defines the Precision Time Protocol (PTP) version 2 (PTPv2). Throughout this manual, PTP is used to refer to this standard. They implement both master clock and ordinary PTP clock functionality. The M68 is a superset of the M64 and additionally implements transparent clock or boundary clock. The M68/M64 feature full connectivity to Gigabit networks with wire-speed cut-through technology, enabling new applications. This document describes how to design with the M68/M64 module and how to use it in embedded applications. The integration section covers the module's pin assignment and other physical aspects such as power supply options. It also describes how to connect the necessary key components that are prerequisites for normal operation. This document applies to M64/M68 software version 3.0. The module can be updated to version 3.0 by following the instructions in Appendix 8: Firmware Upgrade.

Caratteristiche

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  • Low-power microprocessor technology with hardware timestamping
  • 8 MB SDRAM, 2 MB Flash
  • 10/100/1000 Ethernet PHY
  • RGMII interface to host or external PHY
  • Timing interfaces including PPS, TOD, and synchronization frequency
  • Full IEEE 1588-2008 implementation with SyncE support
  • Communication server for serial, Telnet, and SSH
  • Edge pads for SMT to host board
  • RoHS compliant
  • Built-in SNMP server
  • Wire-speed cut-through, eliminating the need for a switch in many applications

Applicazioni

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  • Packet network timing
  • Embedded applications