Intel/Altera EP20K1000CF33C8

APEX 20KC devices offer a MultiCore architecture that combines the advantages of LUT-based and product-term-based devices with an enhanced memory structure. LUT-based logic provides optimized performance and efficiency for datapath, register-intensive, arithmetic, or DSP designs. Product-term-based logic is optimized for complex combinatorial paths such as complex state machines. The combination of LUT and product-term logic with memory functions and a wide variety of MegaCore and AMPP functions makes the APEX 20KC architecture particularly well-suited for system-on-a-programmable-chip (SOPC) designs. Applications that historically required a combination of LUT-, product-term-, and memory-based devices can now be integrated into a single APEX 20KC device. APEX 20KC devices include additional features such as enhanced I/O standard support, content-addressable memory (CAM), additional global clocks, and enhanced ClockLock clock circuitry. All APEX 20KC devices are reconfigurable and are 100% tested before shipment. As a result, there is no need to generate test vectors for fault coverage purposes. Instead, designers can focus on simulation and design verification. Furthermore, designers are not required to manage inventory across different ASIC designs.

• PLD fabricated in 0.15-micron all-layer copper metal process
• 25% to 35% faster design performance than APEX 20KE devices
• Pin-compatible with APEX 20KE devices
• High-performance, low-power copper interconnect
• MultiCore architecture integrating LUT logic and embedded memory
• ESB for memory functions including FIFO buffers, dual-port RAM, and CAM
• High-density architecture offering 200K to 1M typical gates, up to 38,400 LEs
• Up to 327,680 RAM bits without reducing available logic
• Low-power operation at 1.8V supply voltage
• Reduced power consumption via copper interconnect
• MultiVolt I/O supporting 1.8V, 2.5V, and 3.3V interfaces
• ESB programmable power-saving mode
• Flexible clock management circuitry with up to four PLLs
• Built-in low-skew clock tree providing up to eight global clock signals
• ClockLock feature reduces clock latency and skew
• ClockBoost feature provides clock multiplication and division
• ClockShift feature provides programmable clock phase and delay offset
• Robust I/O features compliant with PCI SIG PCI Local Bus Specification Revision 2.2, supporting 33MHz or 66MHz, 32-bit or 64-bit 3.3V operation
• Support for high-speed external memory including DDR SDRAM and ZBT SRAM
• 16 input and 16 output LVDS channels at up to 840Mbps
• I/O pins directly connected to local interconnect for fast setup and hold times in complex logic
• Programmable clamp to VCCIO
• Per-pin independent output tri-state enable control
• Programmable output slew rate control to reduce switching noise
• Support for advanced I/O standards including LVDS, LVPECL, PCI-X, AGP, CTT, SSTL-3 and SSTL-2, GTL+, and HSTL Class I
• Hot-socketing support with I/O pin pull-up before and during configuration
• Copper interconnect for high performance
• Four-level hierarchical FastTrack interconnect structure providing fast, predictable interconnect delays
• Dedicated carry chains for arithmetic functions (e.g., fast adders, counters, and comparators), automatically utilized by software tools and megafunctions
• Dedicated cascade chains for high-speed, high-fan-in logic functions, automatically utilized by software tools and megafunctions
• Interleaved local interconnect allowing one LE to drive 29 other LEs via fast local interconnect
• Software design support and auto place-and-route via Altera Quartus II development system for Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 workstations
• Altera MegaCore functions and Altera Megafunction Partners Program (AMPPSM) megafunctions optimized for APEX 20KC architecture
• NativeLink integration with popular synthesis, simulation, and timing analysis tools
• Quartus II SignalTap embedded logic analyzer simplifies in-system design evaluation by enabling access to internal nodes during device operation
• Support for popular version control packages including PVCS, RCS, and SCCS