Infineon/CYPRESS CY7C1011CV33-12AC

The CY7C1011CV33 is a high-performance CMOS SRAM organized as 131,072 words × 16 bits. To write data to the device, the Chip Enable (CE) and Write Enable (WE) inputs must be driven LOW. When Byte Low Enable (BLE) is LOW, data from the I/O pins (I/O₀–I/O₇) is written to the location specified by the address pins (A₀–A₁₆); when Byte High Enable (BHE) is LOW, data from the I/O pins (I/O₈–I/O₁₅) is written to the location specified by the address pins (A₀–A₁₆). To read data from the device, CE and Output Enable (OE) must be driven LOW while Write Enable (WE) is held HIGH. When BLE is LOW, data from the addressed memory location appears on I/O₀–I/O₇; when BHE is LOW, the stored data appears on I/O₈–I/O₁₅. The I/O pins (I/O₀–I/O₁₅) are placed in a high-impedance state when the device is deselected (CE HIGH), the output is disabled (OE HIGH), both BHE and BLE are disabled (BHE and BLE HIGH), or during a write operation (CE LOW and WE LOW). The CY7C1011CV33 is available in a standard 44-pin TSOP II package (center power and ground pin configuration), a 44-pin Thin Plastic Quad Flat Pack (TQFP), and a 48-ball Very Fine-pitch BGA (VFBGA) package.

• Pin-compatible with CY7C1011BV33
• High speed
• tₐₐ = 10 ns
• 360 mW maximum
• Low active power
• Data retention at 2.0V
• Automatic power-down when deselected
• Independent upper/lower byte control
• Easy memory expansion via CE and OE functions
• Available in 44-pin TSOP II, 44-pin TQFP, and 48-ball VFBGA packages
• Also available in lead-free 44-pin TSOP II and 44-pin TQFP packages