Infineon/CYPRESS CY7C141-55JCT

CY7C130/CY7C131/CY7C140 and CY7C141 are high-speed CMOS 1K x 8 dual-port static RAMs. Two ports are provided, allowing independent access to any location in memory. The CY7C130/CY7C131 can be used as standalone 8-bit dual-port static RAMs, or as master dual-port RAMs in conjunction with slave dual-port devices CY7C140/CY7C141, for systems requiring 16-bit or wider word widths. It is suitable for applications requiring shared or buffered data, such as cache memory in DSP, bit-slice, or multiprocessor designs. Each port has independent control pins: Chip Enable (CE), Write Enable (R/W), and Output Enable (OE). Each port provides two flags: BUSY and INT. BUSY indicates that the port is attempting to access the same location currently being accessed by the other port. INT is an interrupt flag indicating that data has been placed at location (3FF for the left port, 3FE for the right port). The automatic power-down feature is independently controlled by the Chip Enable (CE) pin of each port.

• True dual-port memory cell allowing simultaneous reads of the same memory location
• 1K x 8 organization
• High-speed access: 15 ns
• Low operating power: ICC = 110 mA (max)
• Fully asynchronous operation
• Automatic power-down
• Master CY7C130/CY7C131 easily expandable to 16-bit or wider data bus using slave CY7C140/CY7C141
• BUSY output flag on CY7C130/CY7C131; BUSY input on CY7C140/CY7C141
• INT flag for inter-port communication
• Available in 48-pin DIP (CY7C130/140), 52-pin PLCC, 52-pin TQFP packages
• Lead-free packages available

• Digital Signal Processor (DSP) cache memory
• Bit-slice design
• Multiprocessor design