Infineon/CYPRESS CY7C25682KV18-550BZXI

The CY7C25682KV18, and CY7C25702KV18 are 1.8 V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words (CY7C25682KV18), or 36-bit words (CY7C25702KV18) that burst sequentially into or out of the device. These devices have an On-Die Termination feature supported for D[x:0], BWS[x:0], and K/K inputs, which helps eliminate external termination resistors, reduce cost, reduce board area, and simplify board routing. Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

• 72-Mbit density (4Mx18, 2Mx36)
• ±550 MHz clock for high bandwidth
• Two-word burst for reducing address bus frequency
• Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz
• Available in 2.5 clock cycle latency
• Two input clocks (K and K) for precise DDR timing
• SRAM uses rising edges only
• Echo Clocks (CQ and CQ) simplify data capture in high speed systems
• Data valid pin (QVLD) to indicate valid data on the output
• On-die termination (ODT) feature
• Supported for D[x:0], BWS[x:0], and K/K inputs
• Synchronous internally self-timed writes
• DDR II+ operates with 2.5 cycle read latency when DOFF is asserted HIGH
• Operates similar to DDR I Device with 1 cycle read latency when DOFF is asserted LOW
• Core VDD = 1.8 V ±0.1 V; 1/O VDDQ = 1.4 V to VDD
• Supports both 1.5 V and 1.8 V 1/O supply
• HSTL inputs and variable drive HSTL output buffers
• Available in 165-ball FBGA package (13x15x1.4 mm)
• Offered in both Pb-free and non Pb-free packages
• JTAG 1149.1 compatible test access port
• Phase-locked loop (PLL) for accurate data placement