Infineon/CYPRESS CY9BF166LQN-G-AVE2

Series are highly integrated 32-bit microcontrollers with high performance and competitive cos. This series is based on the Arm Cortex-M4F Processor with on-chip Flash memory and SRAM. The series has perip functions such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I²C, LIN).

• 32-bit Arm Cortex-M4F Core
  • Processor version: r0p1
  • Up to 160 MHz Frequency Operation
  • FPU built-in
  • Support DSP instruction
  • Memory Protection Unit (MPU): improves the reliability of an embedded system
  • Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels
  • 24-bit System timer (Sys Tick): System timer for OS task management
• On-Chip Memories
  • [Flash Memory]
    • MainFlash memory
      • Up to 512 Kbytes
      • Built-in Flash Accelerator System with 16 Kbytes trace buffer memory
      • The read access to Flash memory can be achieved without wait-cycle up to operation frequency of 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System.
      • Security function for code protection
    • WorkFlash memory
      • 32 Kbytes
      • Read cycle:
        • 6 wait-cycle: the operation frequency more than 120 MHz, and up to 160 MHz
        • 4 wait-cycle: the operation frequency more than 72 MHz, and up to 120 MHz
        • 2 wait-cycle: the operation frequency more than 40 MHz, and up to 72 MHz
        • 0 wait-cycle: the operation frequency up to 40 MHz
      • Security function is shared with code protection
  • [SRAM]
    • Composed of three independent SRAMs (SRAM0, SRAM1, and SRAM2). SRAM0 is connected to I-code bus and D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to System bus of Cortex-M4F core.
    • SRAM0: Up to 32 Kbytes
    • SRAM1: Up to 16 Kbytes
    • SRAM2: Up to 16 Kbytes
• Multi-Function Serial Interface (Max 6 Channels)
  • 64 bytes with FIFO (the FIFO step numbers are variable depending on the settings of the communication mode or bit length.)
  • Operation mode is selectable from the followings for each channel.
    • UART
      • Full-duplex double buffer
      • Selection with or without parity supported
      • Built-in dedicated baud rate generator
      • External clock available as a serial clock
      • Hardware Flow control : Automatically control the transmission by CTS/RTS (only ch.4)
      • Various error detect functions available (parity errors, framing errors, and overrun errors)
    • CSIO
      • Full-duplex double buffer
      • Built-in dedicated baud rate generator
      • Overrun error detect function available
      • Serial chip select function (ch.6 only)
      • Supports high-speed SPI (ch.0 and ch.6 only)
      • Data length 5 to 16-bit
    • LIN
      • LIN protocol Rev.2.1 supported
      • Full-duplex double buffer
      • Master/Slave mode supported
      • LIN break field generation (can change to 13 to 16-bit length)
      • LIN break delimiter generation (can change to 1 to 4-bit length)
      • Various error detect functions available (parity errors, framing errors, and overrun errors)
    • I²C
      • Standard mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported
      • Fast mode Plus (Fm+) (Max 1000 kbps, only for ch. 3=ch.A and ch. 4=ch.B) supported
• DMA Controller (8 Channels)
  • DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.
  • 8 independently configured and operated channels
  • Transfer can be started by software