Infineon/CYPRESS CY9BF167MPMC1-G-JNE2

The CY9B160R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the ARM Cortex-M4F Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I²C, LIN).

• 32-bit ARM Cortex-M4F Core
  • Processor version: r0p1
  • Up to 160 MHz Frequency Operation
  • FPU built-in
  • Support DSP instruction
  • Memory Protection Unit (MPU): improves the reliability of an embedded system
  • Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels
  • 24-bit System timer (Sys Tick): System timer for OS task management
• On-chip Memories
  • Flash memory
    • Based on two independent on-chip Flash memories
    • MainFlash memory Up to 1024 Kbytes
      • Built-in Flash Accelerator System with 16 Kbytes trace buffer memory
      • Read access to Flash memory can be achieved without wait-cycle up to operation frequency of 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System
      • Security function for code protection
    • WorkFlash memory
      • 32 Kbytes
      • Read cycle:
        • 6 wait-cycle: the operation frequency more than 120 MHz, and up to 160 MHz
        • 4 wait-cycle: the operation frequency more than 72 MHz, and up to 120 MHz
        • 2 wait-cycle: the operation frequency more than 40 MHz, and up to 72 MHz
        • 0 wait-cycle: the operation frequency up to 40 MHz
      • Security function is shared with code protection
  • SRAM
    • Composed of three independent SRAMs (SRAM0, SRAM1 and SRAM2)
    • SRAM0: Up to 64 Kbytes
    • SRAM1: Up to 32 Kbytes
    • SRAM2: Up to 32 Kbytes
• External Bus Interface
  • Supports SRAM, NOR, NAND Flash and SDRAM device
  • 8-/16-bit Data width
  • Up to 25-bit Address bit
  • Maximum Access size: 256M byte
  • Supports Address/Data multiplex
  • Supports external RDY function
  • Supports scramble function
• Multi-function Serial Interface (Max 8 channels)
  • 64 bytes with FIFO (the FIFO step numbers are variable depending on the settings of the communication mode or bit length)
  • Operation mode is selectable from the followings for each channel:
    • UART
      • Full-duplex double buffer
      • Selection with or without parity supported
      • Built-in dedicated baud rate generator
      • External clock available as a serial clock
      • Hardware Flow control: Automatically control the transmission by CTS/RTS (only ch.4)
      • Various error detect functions available (parity errors, framing errors, and overrun errors)
    • CSIO
      • Full-duplex double buffer
      • Data length 5 to 16-bit
    • LIN
      • LIN protocol Rev.2.1 supported
      • Full-duplex double buffer
      • Master/Slave mode supported
      • LIN break field generation (can change to 13 to 16-bit length)
      • LIN break delimiter generation (can change to 1 to 4-bit length)
      • Various error detect functions available (parity errors, framing errors, and overrun errors)
    • I²C
      • Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported
      • Fast-mode Plus (Fm+) (Max 1000 kbps, only for ch.β = ch.A and ch.7 = ch.B) supported
• DMA Controller (8 channels)
  • DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously
  • 8 independently configured and operated channels
  • Transfer can be started by software or request from the builtin peripherals
  • Transfer address area: 32-bit (4 Gbytes)
  • Transfer mode: Block transfer/Burst transfer/Demand transfer
  • Transfer data type: bytes/half-word/word
  • Transfer block count: 1 to 16
  • Number of transfers: 1 to 65536
• DSTC (Descriptor System Data Transfer Controller) (128 channels)
  • Can transfer data at high-speed without going via the CPU
  • Adopts the Descriptor system and can access directly the memory /peripheral device and performs the data transfer operation following the specified contents of the Descriptor which has already been constructed on the memory
  • Supports the software activation, the hardware activation and the chain activation functions
• A/D Converter (Max 24 channels)
  • 12-bit A/D Converter
    • Successive Approximation type
    • Built-in 3 units
    • Conversion time: 0.5 μs @ 5 V
    • Priority conversion available (priority at 2 levels)
    • Scanning conversion mode
    • Built-in FIFO for conversion data storage (for SCAN conversion: 16 steps, for Priority conversion: 4 steps)
• DA converter (Max 2 channels)
  • R-2R type
  • 12-bit resolution
• Base Timer (Max 8 channels)
  • Operation mode is selectable from the followings for each channel:
    • 16-bit PWM timer
    • 16-bit PPG timer
    • 16-/32-bit reload timer
    • 16-/32-bit PWC timer
• General Purpose I/O Port
  • Can use its pins as general purpose I/O ports when they are not used for external bus or peripherals