Infineon/CYPRESS CY9BF466RPMC-G-MNE2

The CY9B460R Series are a highly integrated 32-bit microcontrollers dedicated for embedded controllers with high-performance and competitive cost. These series are based on the Arm Cortex-M4F Processor with on-chip Flash memory and SRAM, and has peripheral functions such as Motor Control Timers, ADCs and Communication Interfaces (CAN, UART, CSIO, I2C, LIN).

• 32-bit Arm Cortex-M4F Core
  • Processor version: r0p1
  • Up to 160 MHz Frequency Operation
  • FPU built-in
  • Support DSP instruction
  • Memory Protection Unit (MPU): improves the reliability of an embedded system
  • Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels
  • 24-bit System timer (Sys Tick): System timer for OS task management
• On-chip Memories
  • [Flash memory]
    • Based on two independent on-chip Flash memories
    • MainFlash memory: Up to 1024 Kbytes
    • Built-in Flash Accelerator System with 16 Kbytes trace buffer memory
    • The read access to Flash memory can be achieved without wait-cycle up to operation frequency of 72 MHz. Even at the operation frequency more than 72 MHz, an equivalent access to Flash memory can be obtained by Flash Accelerator System.
    • Security function for code protection
    • 6 wait-cycle: the operation frequency more than 120 MHz, and up to 160 MHz
    • 4 wait-cycle: the operation frequency more than 72 MHz, and up to 120 MHz
    • 2 wait-cycle: the operation frequency more than 40 MHz and up to 72 MHz
    • 0 wait-cycle: the operation frequency up to 40 MHz
    • Security function is shared with code protection
  • [SRAM]
    • Composed of three independent SRAMs (SRAM0, SRAM1 and SRAM2). SRAM0 is connected to I-code bus or D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are connected to System bus of Cortex-M4F core.
    • SRAM0: Up to 64 Kbytes; SRAM1: Up to 32 Kbytes; SRAM2: Up to 32 Kbytes
• External Bus Interface
  • Supports SRAM, NOR, NAND Flash and SDRAM device
  • Up to 9 chip selects CS0 to CS8 (CS8 is only for SDRAM)
  • 8-/16-bit Data width
  • Up to 25-bit Address bit
  • Maximum Access size: 256 Mbyte
  • Supports Address/Data multiplex
  • Supports external RDY function
  • Supports scramble function
  • Possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to 0xDFFF_FFFF in 4 Mbytes units.
  • Possible to set two kinds of the scramble key
• CAN Interface (Max 2 channels)
  • Compatible with CAN Specification 2.0A/B
  • Maximum transfer rate: 1 Mbps
  • Built-in 32 message buffer
• Multi-function Serial Interface (Max 8 channels)
  • 64 bytes with FIFO (the FIFO step numbers are variable depending on the settings of the communication mode or bit length.)
  • Operation mode is selectable from UART, CSIO, LIN, I2C for each channel.
  • [UART]
    • Full-duplex double buffer
    • Selection with or without parity supported
    • Built-in dedicated baud rate generator
    • External clock available as a serial clock
    • Hardware Flow control: Automatically control the transmission by CTS/RTS (only ch.4)
    • Various error detect functions available (parity errors, framing errors, and overrun errors)
  • [CSIO]
    • Full-duplex double buffer
    • Built-in dedicated baud rate generator
    • Overrun error detect function available
    • Serial chip select function (ch.6 and ch.7 only)
    • Supports high-speed SPI (ch.4 and ch.6 only)
    • Data length 5 to 16-bit
  • [LIN]
    • LIN protocol Rev.2.1 supported
    • Full-duplex double buffer
    • Master/Slave mode supported
    • LIN break field generation (can change to 13 to 16-bit length)
    • LIN break delimiter generation (can change to 1 to 4-bit length)
    • Various error detect functions available (parity errors, framing errors, and overrun errors)
  • [I2C]
    • Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported
    • Fast-mode Plus (Fm+) (Max 1000 kbps, only for ch. 3= ch.A and ch. '= ch.B) supported
• DMA Controller (8 channels)
  • DMA Controller has an independent bus for CPU, so CPU and DMA Controller can process simultaneously.
  • 8 independently configured and operated channels
  • Transfer can be started by software or request from the builtin peripherals
  • Transfer address area: 32-bit (4 Gbytes)
  • Transfer mode: Block transfer/Burst transfer/Demand transfer
  • Transfer data type: bytes/half-word/word
  • Transfer block count: 1 to 16
  • Number of transfers: 1 to 65536
• DSTC (Descriptor System data Transfer Controller) (128 channels)
  • Can transfer data at high-speed without going via the CPU.
  • Adopts the Descriptor system and, following the specified contents of the Descriptor which has already been constructed on the memory, can access directly the memory /peripheral device and performs the data transfer operation.
  • Supports the software activation, the hardware activation and the chain activation functions.
• A/D Converter (Max 24 channels)
  • [12-bit A/D Converter]
    • Successive Approximation type
    • Built-in 3 units
    • Conversion time: 0.5 μs @ 5 V
    • Priority conversion available (priority at 2 levels)
    • Scanning conversion mode
    • Built-in FIFO