Infineon/CYPRESS S25FS256SDSMFI000

The Cypress S25FS-S family devices are flash non-volatile memory products using:

• MirrorBit technology - that stores two data bits in each memory array transistor
• Eclipse architecture - that dramatically improves program and erase performance
• 65 nm process lithography

The S25FS-S family connects to a host system via a Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional 2-bit

• Density – S25FS128S-128 Mbits (16 Mbytes) – S25FS256S-256 Mbits (32 Mbytes)
• Serial Peripheral Interface (SPI) – SPI Clock polarity and phase modes 0 and 3 – Double Data Rate (DDR) option – Extended Addressing: 24- or 32-bit address options – Serial Command subset and footprint compatible with S25FL-A, S25FL-K, S25FL-P, and S25FL-S SPI families – Multi I/O Command subset and footprint compatible with S25FL-P, and S25FL-S SPI families
• Read – Commands: Normal, Fast, Dual I/O, Quad I/O, DDR Quad I/O – Modes: Burst Wrap, Continuous (XIP), QPI – Serial Flash Discoverable Parameters (SFDP) and Common Flash Interface (CFI), for configuration information
• Program – 256- or 512-byte Page Programming buffer – Program suspend and resume – Automatic ECC – internal hardware Error Correction Code generation with single-bit error correction
• Erase – Hybrid sector option – Physical set of eight 4-kbyte sectors and one 32-kbyte sector at the top or bottom of address space with all remaining sectors of 64 kbytes – Uniform sector option – Uniform 64-kbyte or 256-kbyte blocks for software compatibility with higher density and future devices – Erase suspend and resume – Erase status evaluation – 100,000 Program-Erase Cycles, minimum – 20 Year Data Retention, minimum
• Security Features – One-Time Program (OTP) array of 1024 bytes – Block Protection: – Status Register bits to control protection against program or erase of a contiguous range of sectors – Hardware and software control options – Advanced Sector Protection (ASP) – Individual sector protection controlled by boot code or password – Option for password control of read access
• Technology – Cypress 65 nm MirrorBit Technology with Eclipse Architecture
• Supply Voltage – 1.7V to 2.0V
• Temperature Range / Grade – Industrial -40℃ to +85℃ – Industrial Plus -40℃ to +105℃ – Automotive AEC-Q100 Grade 3 -40℃ to +85℃ – Automotive AEC-Q100 Grade 2 -40℃ to +105℃ – Automotive AEC-Q100 Grade 1 -40℃ to +125℃
• Packages (All Pb-Free) – 8-lead SOIC 208 mil (SOC008) — FS128S only – WSON 6x5 mm (WND008) — FS128S only – WSON 6x8 mm (WNH008) – 16-lead SOIC 300 mil (SO3016 — FS256S only) – BGA-24 6x8 mm – - 5x5 ball (FAB024) footprint -4x6 ball (FAC024) footprint – Known Good Die, and Known Tested Die