Infineon/CYPRESS S27KS0642GABHV020

64Mb HYPERRAM self-refresh DRAM (PSRAM) is a high-speed CMOS, self-refresh DRAM, with HYPERBUS interface. The DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS interface master (host). Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately described as Pseudo Static RAM (PSRAM). Since the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host limit read or write burst transfers lengths to allow internal logic refresh operations when they are needed. The host must confine the duration of transactions and allow additional initial access latency, at the beginning of a new transaction, if the memory indicates a refresh operation is needed.

HYPERBUS is a low signal count, DDR interface, that achieves high-speed read and write throughput. The DDR protocol transfers two data bytes per clock cycle on the DQ[7:0] input/output signals. A read or write transaction on HYPERBUS consists of a series of 16-bit wide, one clock cycle data transfers at the internal HYPERRAM array with two corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ signals. All inputs and outputs are LV-CMOS compatible. Device are available as 1.8 V VCC/(VCCQ or 3.0 V VCC/VCCQ (nominal) for array (VCC) and I/O buffer.

• HYPERBUS interface
• 1.8 V or 3.0 V interface support
• Single-ended clock (CK) - 11 bus signals
• Optional differential clock (CK, CK#) - 12 bus signals
• Chip select (CS#)
• 8-bit data bus (DQ[7:0])
• Hardware reset (RESET#)
• Bidirectional read-write data strobe (RWDS)
• Output at the start of all transactions to indicate refresh latency
• Output during read transactions as Read data strobe
• Input during write transactions as Write data mask
• Optional DDR center-aligned read strobe (DCARS)
• During read transactions RWDS is offset by a second clock, phase shifted from CK
• The phase shifted clock is used to move the RWDS transition edge within the read data eye
• 200 MHz maximum clock rate
• DDR - transfers data on both edges of the clock
• Data throughput up to 400 MBps (3,200 Mbps)
• Configurable burst characteristics: Linear burst
• Wrapped burst lengths: 16 bytes (8 clocks), 32 bytes (16 clocks), 64 bytes (32 clocks), 128 bytes (64 clocks)
• Hybrid option - one wrapped burst followed by linear burst
• Configurable output drive strength
• Power modes - Hybrid Sleep mode - Deep power-down
• Array refresh - Partial memory array (1/8, 1/4, 1/2, and so on) - Full
• Package - 24-ball FBGA
• Operating temperature range - Industrial (I): -40℃ to +85℃ - Industrial Plus (V): -40℃ to +105℃ - Automotive, AEC-Q100 grade 3: -40℃ to +85℃ - Automotive, AEC-Q100 grade 2: -40℃ to +105℃
• Technology - 38-nm DRAM