TI SN74CBT6800CDWR

The SN74CBT6800C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (rₒₙ), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT6800C provides protection for undershoot up to -2V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state. The device also precharges the B port to a user-selectable bias voltage (BIASV) to minimize live-insertion noise. The SN74CBT6800C is a 10-bit bus switch with a single output-enable (ON̅) input. When ON̅ is low, the 10-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When ON̅ is high, the 10-bit bus switch is OFF, and a high-impedance state exists between the A and B ports. The B port is precharged to BIASV through the equivalent of a 10-kΩ resistor when ON̅ is high, or if the device is powered down (Δ(VCC = 0 V)). This device is fully specified for partial-power-down applications using Iₒff. The Iₒff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

• Undershoot Protection for Off-Isolation on A and B Ports Up to −2 V
• B-Port Outputs Are Precharged by Bias Voltage (BIASV) to Minimize Signal Distortion During Live Insertion and Hot-Plugging
• Supports PCI Hot Plug
• Bidirectional Data Flow, With Near-Zero Propagation Delay
• Low ON-State Resistance (rₒₙ) Characteristics (rₒₙ = 3 Ω Typical)
• Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cᵢₒ(OFF) = 5.5 pF Typical)
• Data and Control Inputs Provide Undershoot Clamp Diodes
• Low Power Consumption (Icc = 3 μA Max)
• VCC Operating Range From 4 V to 5.5 V
• Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
• Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs
• Iₒff Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Performance Tested Per JESD 22
  • 2000-V Human-Body Model (A114-B, Class II)
  • 1000-V Charged-Device Model (C101)

• PCI Interface
• Memory Interleaving
• Bus Isolation
• Low-Distortion Signal Gating