Alliance Memory AS4C8M16MSA-6BINTR

The AS4C8M16MSA Family is high-performance CMOS Dynamic RAMs (DRAM) organized as 8M x 16. These devices feature advanced circuit design to provide low active current and extremely low standby current. The device is compatible with the JEDEC standard LP-SDRAM specifications. The Alliance Memory 128Mb SDRAM is a quad-bank DRAM that operates at 1.8V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0 - A11 select the row). The address bits (A0 - A8) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM must be initialized prior to normal operation.

• Standard SDRAM Functionality
• Programmable burst lengths : 1, 2, 4, 8 or full page
• 64ms refresh period (4K cycle)
• JEDEC Compatibility
• Auto TCSR(Temperature Compensated Self Refresh)
• Partial Array Self Refresh power-saving mode
• Deep Power Down Mode
• Driver Strength Control
• Operating Temperature Ranges: - Industrial ( -40 ℃ to +85 ℃ )
• LVCMOS Compatible IO Interface
• 54ball FBGA with 0.800mm ball pitch
• AS4C8M16MSA : Pb-Free & Halogen Free