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ISSI IS42SM16800H-6BLI-TR

Hersteller
ISSIAsian Brands
Herst.-Teilenr.
IS42SM16800H-6BLI-TR
LCSC-Nr.
C2063515
Verp.
TFBGA-54(8x8)
Kundennummer
Hauptmerkm.
128Mbit 3V~3.6V 166MHz TFBGA-54(8x8) Memory RoHS
DatenblattISSI IS42SM16800H-6BLI-TR
RoHS-Konformität1 Dokumente verfügbar
Alternativteile10
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Benachrichtigen
Minimum: 1Vielfaches: 1Verkaufseinheit: Piece
Zur BOM-Liste hinzufügen
Stk.E-Preis(Nur als Referenz)Gesamtbetrag
1+$ 4.4871$ 4.49
200+$ 1.7365$ 347.30
500+$ 1.6763$ 838.15
1,000+$ 1.6455$ 1645.50
Standardgehäuse2500/Full Reel
Besserer Preis bei größerer Menge?
$

Produktspezifikationen

Alle
TypBeschreibung
KategorieIntegrated Circuits (ICs)/Memory/Memory
HerstellerISSI
Verp.TFBGA-54(8x8)
Operating Temperature0℃~+70℃
Refresh Current-
FeaturesHigh-speed clock synchronization;Auto precharge;Auto refresh
Memory Size128Mbit
Voltage - Supply3V~3.6V
Clock Frequency166MHz
Current - Supply-

Beschreibung

KI-Übersetzung

These IS42/45SM/RM/VM16800H are mobile 134,217,728 bits CMOS Synchronous DRAM organized as 4 banks of 2,097,152 words x 16 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input and output voltage levels are compatible with LVCMOS.

In general, this 128Mb SDRAM (2M x 16Bits x 4banks) is a multi-bank DRAM that operates at 3.3V/2.5V/1.8V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16-bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0-BA1 select the bank, A0-A11 select the row). The address bits (BA0-BA1 select the bank, A0-A8 select the column) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized.

Merkmale

KI-Übersetzung
  • JEDEC standard 3.3V, 2.5V, 1.8V power supply
  • Auto refresh and self refresh
  • All pins are compatible with LVCMOS interface
  • 4K refresh cycle / 64ms
  • Programmable Burst Length and Burst Type
  • 1, 2, 4, 8 or Full Page for Sequential Burst
  • 4 or 8 for Interleave Burst
  • Programmable CAS Latency: 2,3 clocks
  • All inputs and outputs referenced to the positive edge of the system clock
  • Data mask function by DQM
  • Internal 4 banks operation
  • Burst Read Single Write operation
  • Special Function Support
  • PASR(Partial Array Self Refresh)
  • Auto TCSR(Temperature Compensated Self Refresh)
  • Programmable Driver Strength Control
  • Full Strength or 1/2, 1/4, of Full Strength
  • Deep Power Down Mode
  • Automatic precharge, includes CONCURRENT Auto Precharge Mode and controlled Precharge

Alternativteile

MPNHerstellerVerpackungVerfügbarkeitStückpreis
IS42SM16800H-6BLIISSITFBGA-54(8x8)0$ 5.4253
IS42RM16800H-6BLI-TRISSITFBGA-54(8x8)0$ 4.8668
IS42S16800E-6BLI-TRISSI54-TFBGA (8x8)0$ 14.0569
IS42S16800F-7BLIISSITFBGA-54(8x8)0$ 9.3408
IS42SM16800H-75BLIISSITFBGA-54(8x8)0$ 7.6288
IS42SM16800H-75BLI-TRISSITFBGA-54(8x8)0$ 4.2726
IS45S16800E-7BLA1-TRISSI54-TFBGA (8x8)0$ 16.5007
IS42S16800E-7BLISSI54-TFBGA (8x8)0$ 13.2397
IS42RM16800H-75BLI-TRISSITFBGA-54(8x8)0$ 4.6229
IS42VM16800H-75BLI-TRISSITFBGA-54(8x8)0$ 7.2456