SILICON LABS C8051F503-IMR

This chip features the following characteristics:

• 12-bit ADC: up to 200ksps sample rate, up to 32 external single-ended inputs, reference voltage sourced from on-chip VREF, external pin, or VDD, selectable internal or external conversion source, built-in temperature sensor.
• Two comparators: programmable hysteresis and response time, configurable as interrupt or reset source, low current.
• On-chip debug: on-chip debug circuit enables full-speed, non-intrusive in-system debugging (no emulator required), supports breakpoints, single-step execution, memory and register inspection/modification, superior to emulation systems using ICE chips, target expansion boards and sockets, low development kit cost.
• Supply voltage: 1.8 to 5.25V. Typical operating current: 19mA at 50MHz; typical stop-mode current: 2μA.
• High-speed 8051 MCU core: pipelined instruction architecture, 70% of instructions execute in 1 or 2 system clocks, peak throughput of 50MIPS at 50MHz clock, extended interrupt handlers.
• Memory: 4352 bytes internal data RAM (256 + 4096 XRAM), 64 or 32kB flash, in-system programmable in 512-byte sectors.
• Digital peripherals: 40, 33, or 25 port I/Os, all 5V-tolerant; CAN 2.0 controller, no crystal required; LIN 2.1 controller (master/slave mode), no crystal required; hardware-enhanced UART, SMBus, and enhanced SPI serial ports; four general-purpose 16-bit counter/timers; 16-bit programmable counter array (PCA) with six capture/compare modules and enhanced PWM.
• Clock sources: internal 24MHz oscillator with ±0.5% accuracy for CAN and master LIN operation; external oscillator supporting crystal, RC, C, or clock (1 or 2-pin mode), real-time clock source switching useful in power-saving modes.
• Package: 48-pin QFP/QFN (C8051F500/1/4/5), 40-pin QFN (C8051F508/9 - F510/1), 32-pin QFP/QFN (C8051F502/3/6/7).
• Automotive qualified: temperature range -40 to +125°C, AEC-Q100 compliant.

• Up to 200ksps
• Up to 32 external single-ended inputs
• VREF from on-chip VREF, external pin or VDD
• Internal or external start of conversion source
• Built-in temperature sensor
• Two Comparators Programmable hysteresis and response time
• Configurable as interrupt or reset source
• Low current
• On-chip debug circuitry facilitates full speed, nonintrusive in-system debug (no emulator required)
• Provides breakpoints, single stepping, inspect/modify memory and registers
• Superior performance to emulation systems using ICE-chips, target pods, and sockets
• Low cost, complete development kit
• Supply Voltage 1.8 to 5.25V
• Typical operating current: 19 mA at 50 MHz; Typical stop mode current: 2 μA
• Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks
• Up to 50 MIPS throughput with 50MHz clock
• Expanded interrupt handler
• 4352 bytes internal data RAM (256 + 4096 XRAM)
• 64 or 32 kB Flash; In-system programmable in 512-byte Sectors
• 40, 33, or 25 Port I/O; All 5V tolerant
• CAN 2.0 Controller—no crystal required
• LIN 2.1 Controller (Master and Slave capable); no crystal required
• Hardware enhanced UART, SMBus, and enhanced SPI serial ports
• Four general purpose 16-bit counter/timers
• 16-Bit programmable counter array (PCA) with six capture/compare modules and enhanced PWM functionality
• Internal 24MHz with ±0.5% accuracy for CAN and master LIN operation
• External oscillator: Crystal, RC, C, or clock (1 or 2 pin modes)
• Can switch between clock sources on-the-fly; useful in power saving modes
• Temperature Range: -40 to +125 °C
• Compliant to AEC-Q100