MICROCHIP MPF050TL-FCSG325I

PolarFire FPGAs are the fifth-generation family of non-volatile FPGA devices, built on state-of-the-art 28 nm non-volatile process technology. Cost-optimized PolarFire FPGAs deliver the lowest power at mid-range densities. PolarFire FPGAs lower the cost of mid-range FPGAs by integrating the industry’s lowest power FPGA fabric, lowest power 12.7 Gbps transceiver lane, built-in low power dual PCI Express Gen2 (EP/RP), and, on select data security (S) devices, an integrated low-power crypto co-processor. PolarFire FPGAs can operate at 1.0 V and 1.05 V, offering the end user the ability to trade off power and performance to match the application requirements.

• Up to 481K logic elements consisting of a 4-input look-up table (LUT) with a fractureable D-type flipflop
• 20 Kb dual- or two-port large static random access memory (LSRAM) block with built-in single error correct double error detect (SECDED)
• 64x12 two-port μpAM block implemented as an array of latches
• 18x18 math block with a pre-adder, a 48-bit accumulator, and an optional 16 deep x 18 coefficient ROM
• Built-in μμμΠμ, modifiable at program time, readable at run time for user data storage
• High-speed serial connectivity with built-in multi-gigabit multi-protocol transceivers from 250 Mbps to 12.7 Gbps
• Integrated dual PCIe for up to x4 Gen2 endpoint (EP) and root port (RP) designs
• High-speed I/O (HSIO) supporting up to 1600 Mbps DDR4, 1333 Mbps DDR3L, and 1333 Mbps LPDDR3/DDR3 memories with integrated |/○ digital
• General purpose I/O (GPIO) supporting 3.3 V, built-in CDR for serial gigabit Ethernet, 1067 Mbps DDR3, and 1600 Mbps LVDS I/O speed with integrated |/○ digital logic
• Low-power phase-locked loops (PLLs) and delay-locked loops (DLLs) for high precision and low-jitter
• 1.0 V and 1.05 V operating modes
• Low device static power
• Low inrush current
• Low power transceivers
• FPGA configuration cells single event upset (SEU) immune
• Built-in SECDED and memory interleaving on LSRAMs
• System controller suspend mode for safety-critical designs
• Cryptography Research Incorporated (CRI)-patented differential power analysis (DPA) bitstream protection
• Integrated physically unclonable function (PUF)
• 56 Kbytes of secure non-volatile memory (sNVM)
• Built-in tamper detectors and countermeasures
• Digest integrity check for FPGA, μPROM, and sNVM
• Data security features in S devices—true random number generator, integrated Athena's TeraFire F5200B Crypto Coprocessor, suite B capable, and CRI DPA countermeasure pass-through license
• Complete FPGA and embedded software development environment
• Includes Synplify Pro synthesis and Mentor ModelSim ME simulation