SKYWORKS SI5382A-C-GM

The Si5381/82 is an ultra high performance wireless jitter attenuator with multiple DSPLLs, optimized for wireless BBU (Baseband Unit) and DU (Distribution Unit) applications. The industry’s first multi-PLL wireless jitter attenuator device is capable of replacing multiple discrete, high performance, VCXO-based jitter attenuators with a fully integrated single chip solution. The featured multi-PLL architecture supports timing paths for Ethernet and CPRI (Common Public Radio Interface) clock cleaning, and generates any low-jitter, general-purpose clocks. The fixed frequency oscillator provides frequency stability for free-run and holdover modes. This all-digital solution provides superior performance that is highly immune to external board disturbances such as power supply noise.

• Supports simultaneous Ethernet, CPRI and general-purpose clocking in a single device
• Input frequency range:
  • Differential: 8 kHz - 750 MHz
  • LVCMOS: 8 kHz to 250 MHz
• Output frequency range:
  • CPRI: up to 2.94912 GHz
  • Other differential: up to 735 MHz
  • LVCMOS: up to 250 MHz
• Ultra-low RMS jitter:
  • 72 fs typ (12 kHz - 20 MHz)
• Phase noise of 122.88 MHz carrier frequency:
  • -118 dBc/Hz @ 100 Hz offset
• ITU-T G.8262 compliant
• Digital frequency synthesis eliminates external VCXO and analog loop filter components
• DSPLL_B supports high-frequency, CPRI clocking. Remaining DSPLLs support Ethernet and general-purposing clocking
• Output frequency range:
  • CPRI: up to 2.94912 GHz with JESD204B support (DSPLL_B)
  • Other differential: up to 735 MHz (DSPLL_A/C/D)
  • LVCMOS: up to 250 MHz
• Ultra-low RMS jitter (12 kHz - 20 MHz):
  • 72 fs typ at 122.88 MHz (DSPLL_B)
  • 88 fs typ at 156.25 MHz (DSPLL_A/C/D)
  • 79 fs typ at 322.265625 MHz (DSPLL_A/C/D)
• Typical phase noise of 122.88 MHz carrier frequency (DSPLL_B):
  • -118 dBc/Hz @ 100 Hz offset
  • -133 dBc/Hz @ 1 kHz offset
  • -142 dBc/Hz @ 10 kHz offset
  • -149 dBc/Hz @ 100 kHz offset
  • -154 dBc/Hz @ 1 MHz offset
• Highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL. CML outputs can be programmed to have 100 - 1600 mVpp single-ended swing.
• Status monitoring (LOS, OOF, LOL)
• Pin controlled input switching
• Optional zero delay mode
• Hitless input clock switching: automatic or manual
• Automatic free-run and holdover modes
• Fastlock feature
• Core voltage:
  • VDD: 1.8 ± 5%
  • VDDA: 3.3 ± 5%
• Independent output clock supply pins: 3.3 V, 2.5 V, or 1.8 V
• Output - output skew: 75 ps max
• Serial interface: I2C or SPI
• In-circuit programmable with non-volatile OT

• Wireless Infrastructure
• eCPRI RRH (Remote Radio Head)
• BBU (Baseband Unit)
• DU (Distribution Unit)
• Test and Measurement