Infineon CY7C265-25WC

The CY7C265 is an 8192×8 registered PROM organized as 8192 words × 8 bits, with integrated pipelined output registers. The device features a programmable initialization byte that can be loaded into the pipeline register via an initialization signal. This initialization byte is the 8193rd byte in the PROM, and its value is programmed at the time of use. The device comes in a 28-pin package with 13 address signals, 8 data output signals, one enable/initialization pin, and one clock pin. The clock functions as the pipeline clock, loading the addressed memory cell contents into the pipeline register on each rising edge. When the output is enabled, data appears at the outputs. The enable/initialization function is implemented through a programmable pin. With asynchronous enable, the outputs can be disabled at any time by driving the enable high, and restored to the active state by driving it low. With synchronous enable, the outputs enter the disabled or high-impedance state on the next positive clock edge after the synchronous enable input goes high. When the synchronous enable pin goes low, the subsequent positive clock edge restores the outputs to the active state. After a positive clock edge, the address and synchronous enable inputs are free to change, since the outputs will not change until the next low-to-high clock transition. This feature allows decoders and sense amplifiers to access the next memory location while the previously addressed data stabilizes at the outputs. If the enable/initialization pin is used for the asynchronous initialization function, the outputs are permanently enabled. The initialization function is useful during power-up and timeout sequences, and facilitates implementation of other complex functions such as a built-in "jump-start" address. When activated, the initialization control input loads the contents of the user-programmed 8193rd 8-bit word into the on-chip register. Each bit is individually programmable, and the initialization function can be used to load any desired combination of 1s and 0s into the register. In the unprogrammed state, activating initialization causes the register to clear. If all bits of the initialization word are programmed to 1, activating initialization performs a register preset. Applying a logic low to the initialization input immediately loads the programmed initialization word into the pipeline register and outputs. A low on the initialization input disables the clock, and the signal must return high to enable the clock independently of all other inputs, including the clock.

• CMOS process for optimal balance between speed and power consumption
• High speed: 15ns address setup time, 12ns clock-to-output time
• Low power: 660mW
• On-chip edge-triggered registers
• Suitable for pipelined microprogram systems
• EPROM technology: 100% programmable; reprogrammable
• Operating voltage: 5V ±10% VCC
• ESD protection exceeding 2001V
• 28-pin, 300-mil plastic or ceramic DIP package