Alliance Memory AS4C128M8D2A-25BCNTR

AS4C128M8D2A is a high-speed CMOS DDR2 SDRAM with a 1024 Mbit capacity and an 8-bit wide data input/output interface. Its internal configuration is a DRAM with 8 banks, i.e., 8 banks × 16Mb address × 8 I/O. The device is designed to comply with the key features of DDR2 DRAM, such as posted CAS# with additive latency, write latency = read latency - 1, off-chip driver (OCD) impedance calibration, and on-die termination (ODT). All control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crossing point of the differential clock (rising edge of CK and falling edge of CK#). All I/O are source-synchronous with a pair of bidirectional strobes (DQS and DQS#). The address bus is used to transfer row, column, and bank address information in a multiplexed RAS#/CAS# fashion. Access begins with the registration of an activate bank command, followed by a read or write command. Read and write accesses to the DDR2 SDRAM are performed in 4-bit or 8-bit burst mode; access starts from the selected location and continues for a programmed number of locations in a programmed sequence. Operating 8 banks in an interleaved manner enables higher random access rates than standard DRAM. Auto-precharge can be enabled to initiate a self-timed row precharge at the end of a burst sequence. Continuous gapless data rates are achievable depending on burst length, CAS latency, and device speed grade. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information on device initialization, register definitions, command descriptions, and device operation. The DDR2 SDRAM must be powered up and initialized in a predefined manner. Failure to follow the specified operating procedures may result in undefined operation. Power-up and initialization require the following sequence: 1. Apply power and attempt to maintain CKE below 0.2×VDDQ with ODT in a low state (all other inputs may be undefined). The VDD voltage ramp time from when VDD rises from 300mV to the minimum VDD must not exceed 200ms; and during the VDD voltage ramp, |VDD - VDDQ| ≤ 0.3V. VDD, VDDL, and VDDQ are driven by a single power converter output; VTT is limited to a maximum of 0.95V; VREF tracks VDDQ / 2. Alternatively, VDD may be applied simultaneously with or before VDD.

• JEDEC compliant
• JEDEC standard 1.8V I/O interface (SSTL_18 compatible)
• Power supply: VDD and VDDQ = +1.8V ± 0.1V
• Operating temperature: TC = 0 ~ 85°C (commercial grade); TC = -40 ~ 95°C (industrial grade)
• JEDEC clock jitter specification compliant
• Fully synchronous operation
• Fast clock rate: 400MHz
• Differential clock, CK and CK#
• Bidirectional single/differential data strobe
• 8 internal banks for concurrent operation
• 4-bit prefetch architecture
• Internal pipelined architecture
• Precharge and active power-down
• Programmable mode and extended mode registers
• Posted CAS# Additive Latency (AL): 0, 1, 2, 3, 4, 5, 6
• Write latency = read latency - 1tCK
• Burst length: 4 or 8
• Burst type: sequential/interleaved
• DLL enable/disable
• Off-chip driver (OCD)
• Impedance calibration
• Adjustable data output drive strength
• ODT
• RoHS compliant
• Auto refresh and self refresh
• 8192 refresh cycles per 64ms
• Average refresh period: 7.8μs (-40°C ≤ TC ≤ +85°C); 3.9μs (+85°C < TC ≤ +95°C)
• 60-ball 8×10×1.2mm (max) FBGA package
• Lead-free and halogen-free