Lattice LFE2-35SE-6FN484C

The LatticeECP2/M series FPGA devices are optimized to deliver advanced DSP blocks, high-speed SERDES (LatticeECP2M series only), and high-speed source-synchronous interfaces in a cost-effective FPGA architecture. This combination is achieved through advances in device architecture and the use of 90nm technology. The LatticeECP2/M FPGA architecture is optimized for high performance and low cost, incorporating LUT-based logic, distributed and embedded memory, PLLs, DLLs, pre-engineered source-synchronous I/O support, enhanced sysDSP blocks, and advanced configuration support including encryption ("S" versions only) and dual-boot capability. The LatticeECP2M device family features high-speed SERDES with PCS. These SERDES with PCS blocks, offering high jitter tolerance and low transmit jitter, can be configured to support a range of popular data protocols including PCI Express, Ethernet (1GbE and SGMII), OBSAI, and CPRI. Transmit pre-emphasis and receive equalization settings make the SERDES suitable for chip-to-chip and small-form-factor backplane applications. Lattice Diamond® design software enables efficient implementation of large, complex designs using the LatticeECP2/M FPGA family. The LatticeECP2/M synthesis library support is compatible with popular logic synthesis tools. The software uses synthesis tool output and constraints from its floorplanning tool to place and route designs in LatticeECP2/M devices. The design tool extracts timing from the routed design and back-annotates it into the design for timing verification. Lattice provides numerous pre-designed IP blocks for the LatticeECP2/M family. By using these IP cores as standardized building blocks, designers can focus on the unique aspects of their designs, thereby improving productivity.

• High logic density for system integration
• 6K to 95K LUTs
• 90 to 583 I/Os
• Embedded SERDES (LatticeECP2M only)
• Data rates 250 Mbps to 3.125 Gbps
• Up to 16 channels per device, supporting PCI Express, Ethernet (1GbE, SGMII), OBSAI, CPRI, and Serial RapidIO
• sysDSP™ blocks
• 3 to 42 blocks for high-performance multiply and accumulate
• Each block supports one 36×36, four 18×18, or eight 9×9 multipliers
• Flexible memory resources
• 55Kbits to 5308Kbits sysMEM™ embedded block RAM
• 18Kbit blocks
• Single-port, pseudo dual-port, and true dual-port
• Byte enable mode support
• 12K to 202Kbits distributed RAM
• Single-port and pseudo dual-port
• sysCLOCK analog PLLs and DLLs
• Two GPLLs and up to six SPLLs per device
• Clock multiplication, division, phase, and delay adjustment
• Dynamic PLL adjustment
• Two general-purpose DLLs per device
• Pre-designed source-synchronous I/O
• DDR registers in I/O cells
• Dedicated gear logic
• Support for source-synchronous standards such as SPI4.2, SFI4 (DDR mode), XGMII
• High-speed ADC/DAC devices
• Dedicated DDR and DDR2 memory support, DDR1: 400 (200MHz) / DDR2: 533 (266MHz)
• Dedicated DQS support
• Programmable sysI/O™ buffers supporting a wide range of interfaces
• LVTTL and LVCMOS 33/25/18/15/12
• SSTL 3/2/18 I, II
• HSTL15 I and HSTL18 I, II
• PCI and differential HSTL, SSTL
• LVDS, RSDS, Bus-LVDS, MLVDS, LVPECL
• Flexible device configuration
• IEEE 1149.1 boundary scan compliant
• Dedicated bank for configuration I/Os
• SPI boot flash interface
• Dual boot image support
• TransFR™ I/O for simple field updates
• Embedded soft error detection macro
• Optional bitstream encryption (LatticeECP2/M "S" versions only)
• System-level support
• ispTRACY™ internal logic analyzer feature
• On-chip oscillator for initialization and general purpose
• 1.2V core supply