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MICROCHIP PIC24FJ128GL405-I/PT

Produttore
MICROCHIP
Cod. Prod.
PIC24FJ128GL405-I/PT
Cod. LCSC
C1015857
Imballo
TQFP-48(7x7)
Numero Cliente
Attr. chiave
PIC 16 Bit 32MHz TQFP-48(7x7) Microcontrollers RoHS
Scheda TecnicaMICROCHIP PIC24FJ128GL405-I/PT
Conformità RoHS2 documenti disponibili
Parti alternative20
Disponibile: 9
9 Pronta consegna
Minimo: 1Multiplo: 1Unità di vendita: Piece
Aggiungi alla Lista BOM
QtàPr. unit.Importo totale
1+$ 6.67$ 6.67
10+$ 6.5096$ 65.10
30+$ 6.4027$ 192.08
100+$ 6.2958$ 629.58
Package Standard250/Full Tray
Prezzo migliore per quantità maggiore?
$

Specifiche del Prodotto

Tutto
TipoDescrizione
CategoriaIntegrated Circuits (ICs)/Embedded/Microcontrollers
ProduttoreMICROCHIP
ImballoTQFP-48(7x7)
ADC (Bit)10bit;12bit
Number of I/O39
Operating Temperature-40℃~+85℃
Voltage - Supply2V~3.6V
Program Memory TypeFLASH
EEPROM-
Program Storage Size128KB
CPU CorePIC
Core Size16 Bit
CPU Maximum Speed32MHz
Oscillator TypeExternal
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Caratteristiche

Traduzione AI
  • Modified Harvard Architecture
  • 512 Kbytes Flash Memory 32 Kbytes RAM Up to 16 MIPS Operation @ 32 MHz
  • 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier
  • 32-Bit by 16-Bit Hardware Divider
  • 16-Bit x 16-Bit Working Register Array C Compiler Optimized Instruction Set Architecture Two Address Generation Units for Separate Read and Write Addressing of Data Memory
  • 64 Segments and 8 Commons Supporting up to 480 Pixels
  • LCD Charge Pump with 5 μA Low Power Core-Independent LCD Animation Operation in Sleep Mode
  • Up to 24-Channel, Software Selectable 10/12-Bit Analog-to-Digital Converter:
    • 12-bit, 350K samples/second conversion rate (single Sample-and-Hold)
    • 10-bit, 400K samples/second conversion rate (single Sample-and-Hold)
    • Sleep mode operation
    • Low-voltage boost for input
    • Band gap reference input feature
    • Core-independent windowed threshold compare feature
    • Auto-scan feature
  • Three Analog Comparators with Input Multiplexing: Programmable reference voltage for comparators
  • 10-Bit, 1 Msps DAC with Buffered Output
  • Sleep and Idle modes Selectively Shut Down: Peripherals and/or core for substantial power reduction and fast wake-up
  • Doze mode Allows CPU to Run at a Lower Clock Speed than Peripherals
  • Alternate Clock modes Allow On-the-Fly: Switching to a lower clock speed for selective power reduction
  • Retention Sleep with On-Chip Ultra Low-Power Retention Regulator
  • Fail-Safe Clock Monitor Operation: Detects clock failure and switches to on-chip, low-power RC Oscillator
  • Power-on Reset (POR), Brown-out Reset (BOR) Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
  • Programmable High or Low-Voltage Detect (HLVD)
  • Flexible Watchdog Timer (WDT) with RC Oscillator for Reliable Operation
  • Deadman Timer (DMT) for Safety-Critical Applications
  • Programmable 32-Bit Cyclic Redundancy Check (CRC) Generator
  • Flash Configurable as OTP by ICSP Write Inhibit
  • CodeGuard Security ECC Flash Memory with Fault Injection: Single Error Correction (SEC) Double-Error Detection (DED)
  • Customer OTP Memory Unique Device Identifier (UDID), 120-Bit Unique ID
  • Supply Voltage Range of 2.0V to 3.6V
  • Operating Ambient Temperature Range of -40°C to +125°C
  • On-Chip Voltage Regulators (1.8V) for Low-Power Operation
  • Large, Dual Partition Flash Program Array:
    • The device’s Flash memory can be configured into two physical sections or a single physical section
    • Capable of holding two independent software applications, including bootloader
    • Permits simultaneous programming of one partition while executing application code from the other
    • Allows run-time switching between Active Partitions
  • Flash Memory: 10,000 erase/write cycle endurance, typical Data retention: 20 years minimum
  • Self-programmable under software control
  • Flash OTP emulation
  • 8 MHz Fast RC Internal Oscillator: Multiple clock divide options Fast start-up
  • 96 MHz PLL Option
  • Programmable Reference Clock Output
  • In-Circuit Serial Programming (ICSP) and In-Circuit Emulation (ICE) via Two Pins
  • JTAG Boundary Scan Support
  • Independent, Low-Power 32 kHz Timer Oscillator
  • Six-Channel DMA Controller: Minimizes CPU overhead and increases data throughput
  • Timer1: 16-Bit Timer/Counter with External Crystal Oscillator; Timer1 can Provide an A/D Trigger
  • Timer2,3,4,5: 16-Bit Timer/Counter, can Create 32-Bit Timer; Timer3 and Timer5 can Provide an A/D Trigger
  • Eight MCCP modules, Each with a Dedicated 16/32-Bit Timer:
    • Three 6-output MCCP modules
    • Five 2-output MCCP modules
  • Four Variable Widths, Serial Peripheral Interface (SPI) Ports on All Devices; Three Operation modes:
    • Three-wire SPI (supports all four SPI modes)
    • Up to 32-byte deep FIFO buffer
    • I2S mode
    • Speed up to 24 MHz
  • Three I²C Master and Slave w/Address Masking, PMBus and IPMI Support
  • Six UART modules:
    • LIN/J2602 bus support (auto-wake-up, Auto-Baud Detect, Break character support)
    • RS-232 and RS-485 support
    • IrDA mode (hardware encoder/decoder functions)
  • Five External Interrupt Pins
  • Hardware Real-Time Clock and Calendar (RTCC)
  • Peripheral Pin Select (PPS) allows Independent I/O Mapping of Many Peripherals
  • Configurable Interrupt-on-Change on All I/O Pins: Each pin is independently configurable for rising edge or falling edge change detection
  • Reference Clock Output with Programmable Divider
  • Four Configurable Logic Cell (CLC) Blocks:
    • Two inputs and one output, all mappable to peripherals or I/O pins
    • AND/OR/XOR logic and D/JK flip-flop functions

Parti alternative

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