GSI Technology GS82582T19GE-450I

GS82582T19/37GE complies with the SigmaDDR-II+ SRAM pin standard for general-purpose input/output synchronous SRAM. They are 301,989,888-bit (288Mb) SRAM devices. The GS82582T19/37GE SigmaDDR-II+ SRAM is an element of a low-power, low-voltage high-speed transceiver logic I/O SRAM family, designed to operate at the required speed for cost-effective, high-performance networking systems.

• 2.0 clock latency
• Synchronous read/write SigmaDDR interface
• General-purpose I/O bus
• JEDEC standard pinout and package
• Double data rate interface
• Byte write control sampled at data input
• Burst length of 2 for reads and writes
• On-chip termination on data, byte write, and clock inputs
• 1.8V ±100mV core supply voltage
• 1.5V or 1.8V HSTL interface
• Pipelined read operation with self-timed delayed write
• Fully coherent read/write pipeline
• ZQ pin for programmable output drive strength
• Data valid pin support
• IEEE 1149.1 JTAG boundary scan compliant
• RoHS-compliant 165-bump BGA package

• Read-dominant applications
• Block transfer applications