ADI AD9516-1BCPZ

The AD9516-1 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an onchip PLL and VCO. The on-chip VCO tunes from 2.30 GHz to 2.65 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used. The AD9516-1 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements. The AD9516-1 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz. Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024. The AD9516-1 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal). The AD9516-1 is specified for operation over the industrial range of -40°C to +85°C.

• Low phase noise, phase-locked loop (PLL)
• On-chip VCO tunes from 2.30 GHz to 2.65 GHz
• External VCO/VCXO to 2.4 GHz optional
• 1 differential or 2 single-ended reference inputs
• Reference monitoring capability
• Automatic revertive and manual reference switchover/holdover modes
• Accepts LVPECL, LVDS, or CMOS references to 250 MHz
• Programmable delays in path to PFD
• Digital or analog lock detect, selectable
• 6 pairs of 1.6 GHz LVPECL outputs
• Each output pair shares a 1-to-32 divider with coarse phase delay
• Additive output jitter: 225 fs rms
• Channel-to-channel skew paired outputs of <10 ps
• 4 pairs of 800 MHz LVDS clock outputs
• Each output pair shares two cascaded 1-to-32 dividers with coarse phase delay
• Additive output jitter: 275 fs rms
• Fine delay adjust (Δt) on each LVDS output
• Each LVDS output can be reconfigured as two 250 MHz CMOS outputs
• Automatic synchronization of all outputs on power-up
• Manual output synchronization available
• 64-lead LFCSP

• Low jitter, low phase noise clock distribution
• 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4
• Forward error correction (G.710)
• Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
• High performance wireless transceivers
• ATE and high performance instrumentation