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Infineon/CYPRESS S29PL032J55BFI120 product image
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Infineon/CYPRESS S29PL032J55BFI120

Hersteller
Infineon/CYPRESS
Herst.-Teilenr.
S29PL032J55BFI120
LCSC-Nr.
C5885227
Verp.
FBGA-48(6.2x8.2)
Kundennummer
Hauptmerkm.
32Mbit 2.7V~3.6V Parallel FBGA-48(6.2x8.2) Memory RoHS
DatenblattInfineon/CYPRESS S29PL032J55BFI120
RoHS-Konformität1 Dokumente verfügbar
Nicht vorrätig
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Minimum: 1Vielfaches: 1Verkaufseinheit: Piece
Zur BOM-Liste hinzufügen
Stk.E-Preis(Nur als Referenz)Gesamtbetrag
1+$ 10.5874$ 10.59
200+$ 4.2247$ 844.94
500+$ 4.0838$ 2041.90
1,000+$ 4.0141$ 4014.10
Standardgehäuse1/Full Tray
Besserer Preis bei größerer Menge?
$

Produktspezifikationen

Alle
TypBeschreibung
KategorieIntegrated Circuits (ICs)/Memory/Memory
HerstellerInfineon/CYPRESS
Verp.FBGA-48(6.2x8.2)
Operating Temperature-40℃~+85℃
FeaturesHardware write protection;Software write protection;Power-on reset
Memory Size32Mbit
Voltage - Supply2.7V~3.6V
Program / Erase Cycles1,000,000 cycles
Clock Frequency-
Data Retention - TDR (Year)20 Years
Block Erase Time(tBE)-
Page Programming Time (Tpp)-
Write Cycle Time(tWC)55ns
InterfaceParallel
Standby Supply Current0.2uA
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KI-Übersetzung
  • Architectural Advantages
    • 128-/64-/32-Mbit Page Mode devices
    • Page size of 8 words: Fast page read access from random locations within the page
    • Single power supply operation
    • Full Voltage range: 2.7 to 3.6 V for read, erase, and program operations for battery-powered applications
    • Simultaneous Read/Write Operation
    • Data can be continuously read from one bank while executing erase/program functions in another bank
    • Zero latency switching from write to read operations
    • FlexBank Architecture (PL127J/PL064J/PL032J)
    • 4 separate banks, with up to two simultaneous operations per device
    • Bank A: PL127J - 16 Mbit (4 Kwx8 and 32 KWx31), PL064J - 8 Mbit (4 KWx8 and 32 Kwx15), PL032J - 4 Mbit (4 Kwx8 and 32 KWx7)
    • Bank B: PL127J - 48 Mbit (32 KWx96), PL064J - 24 Mbit (32 Kwx48), PL032J - 12 Mbit (32 Kwx24)
    • Bank C: PL127J - 48 Mbit (32 Kwx96), PL064J - 24 Mbit (32 Kwx48), PL032J - 12 Mbit (32 Kwx24)
    • Bank D: PL127J - 16 Mbit (4 Kwx8 and 32 KWx31), PL064J - 8 Mbit (4 Kwx8 and 32 Kwx15), PL032J - 4 Mbit (4 Kwx8 and 32 KWx7)
    • Enhanced Versatile I/O (VIO) Control
    • Output voltage generated and input voltages tolerated on all control inputs and I/Os is determined by the voltage on the VIO pin
    • VIO options at 1.8 V and 3 V I/O for PL127J devices
    • 3 V VIO for PL064J and PL032J devices
    • Secured Silicon Sector region
    • Up to 128 words accessible through a command sequence
    • Up to 64 factory-locked words
    • Up to 64 customer-lockable words
    • Both top and bottom boot blocks in one device
    • Manufactured on 110-nm process technology
    • Data Retention: 20 years typical
    • Cycling Endurance: 1 million cycles per sector typical
  • Performance Characteristics
    • High Performance
    • Page access times as fast as 20 ns
    • Random access times as fast as 55 ns
    • Power consumption (typical values at 10 MHz)
    • 45 mA active read current
    • 17 mA program/erase current
    • 0.2 μA typical standby mode current
  • Software Features
    • Software command-set compatible with JEDEC 42.4 standard
    • Backward compatible with Am29F, Am29LV, Am29DL, and AM29PDL families and MBM29QM/RM, MBM29LV, MBM29DL, MBM29PDL families
    • CFI (Common Flash Interface) compliant
    • Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices
    • Erase Suspend / Erase Resume
    • Suspends an erase operation to allow read or program operations in other sectors of same bank
    • Program Suspend / Program Resume
    • Suspends a program operation to allow read operation from sectors other than the one being programmed
    • Unlock Bypass Program command
    • Reduces overall programming time when issuing multiple program command sequences
  • Hardware Features
    • Ready/Busy# pin (RY/BY#)
    • Provides a hardware method of detecting program or erase cycle completion
    • Hardware reset pin (RESET#)
    • Hardware method to reset the device to reading array data
    • WP#/ ACC (Write Protect/Acceleration) input
    • At VIL, hardware level protection for the first and last two 4K word sectors.
    • At VIH, allows removal of sector protection
    • At VHH, provides accelerated programming in a factory setting
    • Persistent Sector Protection
    • A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector
    • Sectors can be locked and unlocked in-system at VCC level
    • Password Sector Protection
    • A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password
    • Package Options
    • 11x8 mm, 80-ball Fine-pitch BGA (PL127J) (VBG080)
    • 8.15x6.15 mm, 48-ball Fine pitch BGA (PL064J/PL032J) (VBK048)
    • 20x14 mm, 56-pin TSOP (PL127J) (TS056)