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Nexperia 74LVC8T595BQX

Produttore
Cod. Prod.
74LVC8T595BQX
Cod. LCSC
C548860
Imballo
DHVQFN-20-EP(2.5x4.5)
Numero Cliente
Attr. chiave
1.1V~5.5V 24mA 4.1ns@5V,50pF Serial-to-Serial or Parallel DHVQFN-20-EP(2.5x4.5) Shift Registers RoHS
Scheda TecnicaNexperia 74LVC8T595BQX
Conformità RoHS1 documenti disponibili
Disponibile: 12,000
12,000 Pronta consegna
Minimo: 1Multiplo: 1Unità di vendita: Piece
Aggiungi alla Lista BOM
QtàPr. unit.Importo totale
1+$ 0.9719$ 0.97
10+$ 0.785$ 7.85
30+$ 0.69$ 20.70
100+$ 0.5982$ 59.82
500+$ 0.5425$ 271.25
1,000+$ 0.513$ 513.00
Package Standard3000/Full Reel
Prezzo migliore per quantità maggiore?
$

Specifiche del Prodotto

Tutto
TipoDescrizione
CategoriaIntegrated Circuits (ICs)/Logic/Shift Registers
ProduttoreNexperia
ImballoDHVQFN-20-EP(2.5x4.5)
Operating temperature-40℃~+125℃
Pd - Power Dissipation500mW
Voltage - Supply1.1V~5.5V
Output TypeTri-State
Current - Output High(IOH)24mA
Series74LVC
Current - Output Low(IOL)24mA
Output Current24mA
FeaturesAsynchronous clear function;Output enable
Propagation Delay4.1ns@5V,50pF
FunctionSerial-to-Serial or Parallel

Descrizione

Traduzione AI

The 74LVC8T595 is an 8-bit serial-in, serial-or-parallel-out shift register with storage register and 3-state outputs. The shift register and storage register have separate clocks. Data is shifted on the rising edge of the SHCP input. On the rising edge of the STCP input, the data in the shift register is transferred to the storage register. If the two clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. VCC(A) and VCC(B) can be powered at any voltage between 1.1V and 5.5V, making the device suitable for translation between any voltage nodes (1.2V, 1.5V, 1.8V, 2.5V, 3.3V, and 5.0V). Pins MR̄, SHCP, STCP, OE̅, DS, and Q7S are referenced to VCC(A), and pins Qn are referenced to VCC(B). The device is fully specified for partial power-down applications using IOFF. The IOFF circuit disables the outputs, preventing any damaging backflow current through the device when it is powered down. In standby mode, when VCC(A) is at ground level, the Qn outputs are in a high-impedance off state.

Caratteristiche

Traduzione AI
  • Wide supply voltage range: VCC(A): 1.1V to 5.5V; VCC(B): 1.1V to 5.5V
  • High noise immunity
  • Standby mode
  • Latch-up performance exceeds 100mA per JESD 78 Class II
  • ±24mA output drive (VCC(A)=VCC(B)=3.0V)
  • Inputs accept voltages up to 5.5V
  • IOFF circuitry supports partial power-down mode operation
  • JEDEC standards compliant: JESD8-12A (1.1V to 1.3V), JESD8-11A (1.4V to 1.6V), JESD8-7 (1.65V to 1.95V), JESD8-5 (2.3V to 2.7V), JESD8C (3.0V to 3.6V), JESD12-6 (4.5V to 5.5V)
  • ESD protection: HBM: exceeds 4000V per ANSI/ESDA/JEDEC JS-001 Class 3A; CDM: exceeds 1000V per ANSI/ESDA/JEDEC JS-002 Class C3
  • Operating temperature range: -40°C to +85°C and -40°C to +125°C