Nexperia 74LVC2G38DP,125

The 74LVC2G38 is a dual 2-input NAND gate with open-drain outputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

• Wide supply voltage range from 1.65 V to 5.5 V
• 5 V tolerant outputs for interfacing with 5 V logic
• Overvoltage tolerant inputs to 5.5 V
• High noise immunity
• CMOS low power dissipation
• IOFF circuitry provides partial Power-down mode operation
• ±24 mA output drive (VCC = 3.0 V)
• Open-drain outputs
• Latch-up performance exceeds 250 mA
• Direct interface with TTL levels
• Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD36 (4.5 V to 5.5 V)
• ESD protection:
  • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
  • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and -40 °C to +125 °C

• Level translation in mixed 3.3V and 5V environments
• Interface with 5V logic
• Direct TTL-level interface