Infineon/CYPRESS S6E2D35G0AGV20000

Devices in the S6E2D3 Series are highly integrated 32-bit microcontrollers with high performance and competitive cost. This series is based on the Arm Cortex-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral functions such as graphics engine, display controller, motor control timers, ADCs, and Communication Interfaces (USB, UART, CSIO, I²C, LIN).

• 32-bit Arm Cortex-M4F Core
  • Processor version: r0p1
  • Up to 160 MHz frequency operation
  • Built-in FPU
  • Supports DSP instructions
  • Memory Protection Unit (MPU): improves the reliability of an embedded system
  • Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 128 peripheral interrupts and 16 priority levels
  • 24-bit system timer (Sys Tick): System timer for OS task management
• On-Chip Memories
  • Flash memory
    • 384 Kbytes
    • Built-in Flash Accelerator System with 16 Kbytes trace buffer memory
    • Security function for code protection
  • SRAM
    • SRAM0: 32 Kbytes
    • SRAM2: 4 Kbytes
  • VRAM
    • Max 512 Kbytes
  • VFLASH
    • S6E2D35GJA is equipped with a Flash for GDC: 2 Mbytes
• External Bus Interface
  • Supports SRAM, NOR, NAND Flash and SDRAM devices
  • Up to two chip selects CS0 and CS8 (CS8 is only for SDRAM)
  • 8-/16-bit data width
  • Up to 25-bit address bit
  • Maximum area size: Up to 256 Mbytes
  • Supports address/data multiplexing
  • Supports external RDY function
  • Supports the scramble function
    • Possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to 0x7FFF_FFFF in 4 Mbytes units
    • Possible to set two kinds of the scramble key
• USB Interface (One channel)
  • USB device
    • USB2.0 Full-Speed supported
    • Max 6 EndPoint supported
      • EndPoint 0 is for control transfer
      • EndPoint 1, 2 can be selected for bulk-transfer, interrupt-transfer or isochronous-transfer
      • EndPoint 3 to 5 can select bulk-transfer or interrupt-transfer
    • EndPoint 1 to 5 comprise the double buffer
    • The size of each endpoint:
      • Endpoint 0, 2 to 5: 64 bytes
      • EndPoint 1: 256 bytes
  • USB host
    • USB2.0 Full-Speed / Low-Speed supported
    • Bulk-transfer, interrupt-transfer and isochronous-transfer support
    • USB device connected/disconnected automatically detect
    • In/out token handshake packet automatically accepted
    • Max 256-byte packet-length supported
    • Wake-up function supported
• Multi-function Serial Interface (Max eight channels)
  • 64 bytes with FIFO (the FIFO step numbers vary depending on the settings of the communication mode or bit length)
  • Operation mode is selectable from the following for each channel:
    • UART
      • Full-duplex double buffer
      • Selection with or without parity supported
      • Built-in dedicated baud rate generator
      • External clock available as a serial clock
      • Various error detect functions available (parity errors, framing errors, and overrun errors)
    • CSIO
      • Full-duplex double buffer
      • Built-in dedicated baud rate generator
      • Overrun error detect function available
      • Serial chip select function (ch.6 and ch.7 only)
      • Supports High-speed SPI (ch.6 only)
      • Data length 5 to 16-bit
    • LIN
      • LIN protocol Rev.2.1 supported
      • Full-duplex double buffer
      • Master/Slave mode supported
      • LIN break field generation (can change to 13 to 16-bit length)
      • LIN break delimiter generation (can change to 1 to 4-bit length)
      • Various error detect functions available (parity errors, framing errors, and overrun errors)
    • I²C
      • Standard mode (Max 100 kbps) / Fast mode (Max 400 kbps) supported
      • Fast mode Plus (Fm+) (Max 1000 kbps, only for ch. 4 = ch.A) supported
• DMA Controller (Eight channels)
  • The DMA controller has an independent bus for the CPU, so the CPU and the DMA controller can process simultaneously
  • 8 independently configured and operated channels
  • Transfer can be started by software or requested from the built-in peripherals
  • Transfer address area: 32-bit (4 Gbytes)
  • Transfer mode: Block transfer/Burst transfer/Demand transfer
  • Transfer data type: bytes/half-word/word
  • Transfer block count: 1 to 16
  • Number of transfers: 1 to 65536
• DSTC (Descriptor System Data Transfer Controller) (128 channels)
  • The DSTC can transfer data at high-speed without going via the CPU. The DSTC adopts the descriptor system and, following the specified contents of the descriptor that has already been constructed