MICROCHIP ZL30116GGG2V2

The ZL30116 SONET/SDH System Synchronizer is a highly integrated device that provides the functionality required for synchronizing network equipment. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides a wide variety of synchronized output clocks and frame pulses.

• Supports the requirements of Telcordia GR-253 and GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and the requirements of ITU-T G.781 SETS, G.813 SEC, G.823, G.824 and G.825 clocks
• Internal APLL provides standard output clock frequencies up to 622.08 MHz that meet jitter requirements for interfaces up to OC-192/STM-64
• Programmable output synthesizers generate clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz
• Provides two DPLLs which are independently configurable through a serial software interface
• DPLL1 provides all the features necessary for generating SONET/SDH compliant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), selectable loop bandwidth and pull-in range
• DPLL2 provides a comprehensive set of features necessary for generating derived output clocks and other general purpose clocks
• Provides 8 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz
• Supports master/slave configuration for AdvancedTCA M
• Configurable input to output delay and output to output phase alignment
• Optional external feedback path provides dynamic input to output delay compensation
• Provides 3 sync inputs for output frame pulse alignment
• Generates several styles of output frame pulses with selectable pulse width, polarity and frequency
• Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities
• Supports IEEE 1149.1 JTAG Boundary Scan

• AdvancedTCATM Systems
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• Wireless/Wireline Gateways
• Wireless Base Stations
• DSLAM / Next Gen DLC
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