ADI ADSP-SC571BSWZ-3

The ADSP-SC57x/ADSP-2157x processors belong to the SHARC product family. The processors are based on SHARC+ dual-core and ARM Cortex-A5 cores. The ADSP-SC57x/ADSP-2157x processors are SIMD SHARC family DSPs featuring a Super Harvard architecture. These 32/40/64-bit floating-point processors are optimized for high-performance audio/floating-point applications, offering large on-chip SRAM, multiple internal buses to eliminate I/O bottlenecks, and an innovative Digital Audio Interface (DAI). The latest enhancements to the SHARC+ core include cache improvements, branch prediction, and other instruction set enhancements while maintaining instruction set compatibility with previous SHARC products. This ARM/SHARC processor integrates numerous industry-leading system peripherals and memory, delivering programmability, multimedia support, and advanced signal processing in a single integrated package — making it an ideal platform for next-generation applications. These applications span a wide range of markets, from automotive and professional audio to industrial applications requiring high-performance floating-point processing.

• Dual enhanced SHARC+ high-performance floating-point cores, each up to 450 MHz
• Up to 3 Mb (384 kB) L1 SRAM per core with parity support, configurable as cache (optional feature)
• 32-bit, 40-bit, and 64-bit floating-point and fixed-point byte, short word, word, and long word addressing
• Core 450 MHz/720 DMIPS with Neon/VFPv4-D16/Jazelle support
• 32 kB L1 instruction cache with parity/32 kB L1 data cache with parity
• 256 kB L2 cache with parity support
• Robust DMA system
• On-chip memory protection
• Integrated safety features
• 17 mm × 17 mm 400-pin CSP BGA and 176-pin LQFP-EP packages, RoHS compliant
• Low system power consumption, automotive temperature range
• Up to 1 MB on-chip L2 SRAM with ECC protection
• One L3 interface optimized for low system power, providing a 16-bit interface to DDR3, DDR2, or external devices
• L1 instruction and data cache units (32/32 kB)
• In-order pipeline with dynamic branch prediction
• ARM, Thumb, and ThumbEE instruction set security extensions support
• Harvard L1 memory system with MMU
• Debug architecture
• Trace support via ETM interface
• Extension: VFP unit with non-trapping execution (IEEE 754)
• Extension: Media Processing Engine (MPE) with NEON technology
• Extension: Jazelle hardware acceleration

• Automotive
• Professional Audio
• Industrial Applications