Infineon/CYPRESS CY8C6144LQI-S4F92

PSoC 6 MCU is a high-performance, ultra-low-power and secured MCU platform, purpose-built for IoT applications. The CY8C61x4 product line, based on the PSoC 6 MCU platform, is a combination of a dual CPU microcontroller with low-power flash technology, digital programmable logic, high-performance analog-to-digital conversion and standard communication and timing peripherals.

• 150-MHz Arm Cortex-M4F (CM4) with single-cycle multiply (Floating Point and Memory Protection Unit)
• 100-MHz Cortex-M0+ with single-cycle multiply and MPU
• User-selectable core logic operation at either 1.1V or 0.9V
• Active CPU current slope with 1.1-V core operation: Cortex-M4: 40 µA/MHz; Cortex-M0+: 20 µA/MHz
• Active CPU current slope with 0.9-V core operation: Cortex-M4: 2 µA/MHz; Cortex-M0+: 15 µA/MHz
• Three DMA controllers
• 256-KB application flash and 32-KB supervisory flash (SFlash); read-while-write (RWW) support. Two 8-KB flash caches, one for each CPU.
• 128-KB SRAM with programmable power control and retention granularity
• One-time-programmable (OTP) 1-Kb eFuse array
• Six power modes for fine-grained power management
• Deep Sleep mode current of 7 µA with 64-KB SRAM retention
• On-chip DC-DC Buck converter, <1-µA quiescent current
• Backup domain with 64 bytes of memory and real-time clock
• 8-MHz internal main oscillator (IMO) with ±2% accuracy
• Ultra-low-power 32-kHz internal low-speed oscillator (ILO)
• On-chip crystal oscillators (16 to 35 MHz, and 32 kHz)
• Phase-locked loop (PLL) for multiplying clock frequency
• Frequency-locked loop (FLL) for multiplying IMO frequency
• Execute-In-Place (XIP) from external Quad SPI Flash
• On-the-fly encryption and decryption
• 4-KB cache for greater XIP performance with lower power
• Supports single, dual, and quad interfaces with throughput up to 320 Mbps
• Supports up to 61 segments and up to 8 commons
• Operates in System Deep Sleep mode
• Six run-time configurable serial communication blocks (SCBs)
• Five SCBs: configurable as SPI, I2C, or UART
• One Deep Sleep SCB: configurable as SPI or I2C
• USB Full-Speed device interface
• One CAN FD block
• Twelve timer/counter pulse-width modulators (TCPWMs)
• Center-aligned, Edge, and Pseudo-random modes
• Comparator-based triggering of Kill signals
• Two 12-bit 2-Msps SAR ADCs with synchronized sampling, differential and single-ended modes, 16-channel sequencer with result averaging, and Deep Sleep operation
• One 12-bit voltage-mode digital-to-analog converter (DAC) with <2-μs settling time
• Two low-power comparators available in Deep Sleep and Hibernate modes
• Two opamps with low-power operation modes
• Always-on low frequency Deep Sleep operation
• Built-in temperature sensor connected to ADC
• One Smart I/O port (6 I/Os) enables Boolean operations on GPIO pins; available during system Deep Sleep
• Programmable drive modes, strengths, and slew rates
• Two overvoltage-tolerant (OVT) pins
• Cypress CapSense Sigma-Delta (CSD) provides best-in-class SNR, liquid tolerance, and proximity sensing
• Enables dynamic usage of both self and mutual sensing
• Automatic hardware tuning (SmartSense)
• Authentication during boot using hardware hashing
• All debug and test ingress paths can be disabled
• Up to eight protection contexts
• Hardware acceleration for symmetric and asymmetric cryptographic methods and hash functions
• True random number generation (TRNG) function