TI TMS320DM6435ZWT6

The TMS320C64x+™ DSPs (including the TMS320DM6435 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6435 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture, making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

With performance of up to 5600 million instructions per second (MIPS) at a clock rate of 700 MHz, the Gfx+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The Gfx+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2800 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5600 MMACS.

The DM6435 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6435 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space —384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way

• High-Performance Digital Media Processor
• 2.5-, 2.-, 1.67-,1.51-, 1.43-ns Instruction Cycle Time
• 400-, 500-, 600-, 660-, 700-MHz C64x+7M Clock Rate
• Eight 32-Bit cex+ Instructions/Cycle
• 3200, 4000, 4800, 5280, 5600 MIPS
• Fully Software-Compatible With c64x
• Commercial and Automotive (Q or S suffix) Grades
• Low Power Device (L suffix)
• Byte-Addressable (8-/16-/32-/64-Bit Data)
• 8-Bit Overflow Protection
• Bit-Field Extract, Set, Clear
• Normalization, Saturation, Bit-Counting
• VelociTI.2 Increased Orthogonality
• c64x+ Extensions
• Compact 16-bit Instructions
• Additional Instructions to Support Complex Multiplies
• 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
• 640K-Bit (80K-Byte) L1D Data RAM/Cache [Flexible Allocation]
• 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
• Supports Little Endian Mode Only
• CCD and CMOS Imager Interface
• BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
• Preview Engine for Real-Time Image Processing
• Glueless Interface to Common Video Decoders
• Histogram Module
• Auto-Exposure, Auto-White Balance and Auto-Focus Module
• Resize Engine – Resize Images From 1/4x to 4x
• Separate Horizontal/Vertical Control
• 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
• Supports up to 333-MHz (data rate) bus and interfaces to DDR2-400 SDRAM
• Asynchronous 8-Bit Wide EMIF (EMIFA) With up to 64M-Byte Address Reach
• Flash Memory Interfaces – NOR (8-Bit-Wide Data) – NAND (8-Bit-Wide Data)
• Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
• Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
• One 64-Bit Watch Dog Timer
• Two UARTs (One with RTS and CTS Flow Control)
• Master/Slave Inter-Integrated Circuit I²C Bus
• Multichannel Buffered Serial Port (McBSP) – I2S and TDM – AC97 Audio Codec Interface
• SPI Standard Voice Codec Interface (AIC12)
• Telecom Interfaces – ST-Bus, H-100 128 Channel Mode
• Multichannel Audio Serial Port (McASP0) – Four Serializers and SPDIF (DIT) Mode
• 16-Bit Host-Port Interface (HPI)
• High-End CAN Controller (HECC)
• 10/100 Mb/s Ethernet MAC (EMAC) – IEEE 802.3 Compliant
• Supports Media Independent Interface (MII)
• Management Data I/O (MDIO) Module
• VLYNQ™Interface (FPGA Interface)
• Three Pulse Width Modulator (PWM) Outputs
• On-Chip ROM Bootloader
• Individual Power-Savings Modes
• Flexible PLL Clock Generators
• IEEE-1149.1 (JTAG™)
• Boundary-Scan-Compatible
• Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
• 3.3-V and 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-L/-Q6/-Q5/-Q4)
• 3.3-V and 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5)

• Digital Media
• Networked Media
• Encode Video
• Imaging