TI SN74LV4T125PWR

SN74LV4T125 is a low-voltage CMOS buffer gate that operates at a wider voltage range for portable, telecom, industrial, and automotive applications. The output level is referenced to the supply voltage and is able to support 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels. The input is designed with a lower threshold circuit to match 1.8 V input logic at VCC = 3.3 V and can be used in 1.8 V to 3.3 V level-up translation. In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output at VCC = 2.5 V). The wide VCC range of 1.8 V to 5.5 V allows the generation of desired output levels to connect to controllers or processors. The SN74LV4T125 device is designed with current-drive capability of 8 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs. Supports Standard Logic Pinouts CMOS Output B Compatible with AUP125, LVC125

• Single-supply voltage translation; supply voltage options: 5.0V, 3.3V, 2.5V, 1.8V
• Operating voltage range: 1.8V~5.5V
• Up-level translation support; translation ranges: 1.2V~1.8V (VCC = 1.8V), 1.5V~2.5V (VCC = 2.5V), 1.8V~3.3V (VCC = 3.3V), 3.3V~5.0V (VCC = 5.0V)
• Down-level translation support; translation ranges: 3.3V~1.8V (VCC = 1.8V), 3.3V~2.5V (VCC = 2.5V), 5.0V~3.3V (VCC = 3.3V)
• Logic output levels referenced to VCC
• Up to 50MHz operation at 3.3V VCC
• Input pins tolerant to 5.5V
• Operating temperature range: -40℃~125℃
• Lead-free package option available; SC-70(RGY) package dimensions: 3.5×3.5×1mm
• Latch-up performance exceeds 250mA, compliant with JESD 17
• ESD performance per JESD 22: HBM 2000V (A114-B, Class II), MM 200V (A115-A), CDM 1000V (C101)
• Standard logic pinout compatible
• CMOS output compatible with AUP125, LVC125
• 8mA output drive capability, reducing line reflections, overshoot, and undershoot caused by high-drive outputs

• Tablet
• Smartphone
• Personal Computer
• Industrial
• Automotive