ADI AD9887AKSZ-100

The AD9887 offers designers the flexibility of a dual analog and digital interface for flat panel displays (FPDs) on a single chip. Both interfaces are optimized for excellent image quality supporting display resolutions up to SXGA 1280×1024 at 75 Hz. Either the analog or the digital interface can be selected by the user.

The AD9887 is a fully integrated interface solution for FPDs. It includes an analog interface with a 140 MHz triple ADC with internal 1.25 V reference, PLL to generate a pixel clock from HSYNC, programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and HSYNC. Three - state CMOS outputs may be powered from 2.5 V to 3.3 V.

The AD9887’s on - chip PLL generates a pixel clock from HSYNC. Pixel clock output frequencies range from 12 MHz to 140 MHz. PLL clock jitter is 500 ps p - p typical at 140 MSPS. When a COAST signal is presented, the PLL maintains its output frequency in the absence of HSYNC. A sampling phase adjustment is provided. Data, HSYNC and Clock output phase relationships are maintained. The PLL can be disabled and an external clock input provided as the pixel clock. The AD9887 also offers full sync processing for composite sync and sync - on - green applications.

A clamp signal is generated internally or may be provided by the user through the CLAMP input pin. The analog interface is fully programmable via a 2 - wire serial interface.

The AD9887 contains a Digital Video Interface (DVI 1.0) compatible receiver. This receiver supports displays ranging from VGA to SXGA (25 MHz to 112 MHz). The receiver operates with true color (24 - bit) panels in 1 or 2 pixel(s)/clock mode, and also features an intrapair skew tolerance up to one full clock cycle.

Fabricated in an advanced CMOS process, the AD9887 is provided in a 160 - lead MQFP surface mount plastic package and is specified over the 0℃ to 70℃ temperature range.

• Analog Interface
• 140 MSPS Maximum Conversion Rate
• 330 MHz Analog Bandwidth
• 0.5 V to 1.0 V Analog Input Range
• 500 ps p - p PLL Clock Jitter at 140 MSPS
• 3.3 V Power Supply
• Full Sync Processing
• Midscale Clamp
• 4:2:2 Output Format Mode
• Digital (DVI 1.0 Compatible) Interface
• 112 MHz Operation (1 Pixel/Clock Mode)
• High Skew Tolerance of One Full Input Clock
• Sync Detect for “Hot Plugging”

• RGB Graphics Processing
• LCD Monitors and Projectors
• Plasma Display Panels
• Scan Converters
• Micro Displays
• Digital TV