ADI AD7581LNZ

The AD7581 is a microprocessor compatible 8 bit, 8 channel, memory buffered, data - acquisition system on a monolithic CMOS chip. It consists of an 8 bit successive approximation A/D converter, an 8 channel multiplexer, 8×8 dual - port RAM, three - state DATA drivers (for interface), address latches and microprocessor compatible control logic. The device interfaces directly to 8080,8085, Z80,6800 and other micro - processor systems. The successive approximation conversion takes place on a continuous, channel sequencing, basis using microprocessor control signals for the clock. Data is automatically transferred to its proper location in the 8×8 dual - port RAM at the end of each conversion. When under microprocessor control, a READ DATA operation is allowed at any time for any channel since on - chip logic provides interleaved DMA. The facility to latch the address inputs (A₀ - A₂) with ALE enables the AD7581 to interface with μP systems which feature either shared or separate address and data buses. The AD7581 accepts eight analog inputs and sequentially converts each input into an eight - bit binary word using the successive approximation technique. The conversion results are stored in an 8×8 bit dual - port RAM. The device runs either directly from the microprocessor clock (in 6800 type systems) or from some suitable signal (e.g. ALE in 8085 type systems). Most applications require only a - 10v reference and a + 5v supply. Start - up logic is included on the device to establish the correct sequences on power - up. A maximum of 800 clock pulses are required for this period. Conversion of a single channel requires 80 input clock periods and a complete scan through all channels requires 640 input clock periods. When a channel conversion is complete, the successive approximation register contents are loaded into the proper channel location of the 8 X 8 RAM. At this time a status signal output, STAT (pin 12), gives a short negative going pulse (8 clock periods). This negative going STAT pulse is extended to 72 clock periods when channel 1 conversion is complete. An external pulse - width detector connected to the status pin can be used to derive conversion - related timing signals for microprocessor interrupts. Simultaneous with STAT going low, the MUX address is decremented. Eight clock periods later the next conversion is started. Automatic interleaved DMA is provided by on - chip logic to ensure that memory updates take place at instants when the microprocessor is not addressing memory. Memory locations are addressed by A₀, A₁ and A₂. This address may be latched by ALE for systems which feature a multiplexed address/data bus or alternatively, for systems which have separate address and data buses, the address latches can be made transparent by tying ALE (pin 16) HIGH. CS (pin 13) activates three - state buffers to place addressed data on the DB₀ - DB₇ data output pins.

• 8 - Bit Resolution
• On - Chip 8 X 8 Dual - Port Memory
• No Missed Codes Over Full Temperature Range
• Interfaces Directly to Z80/8085/6800
• CMOS, TTL Compatible Digital inputs
• Three - State Data Drivers
• Ratiometric Capability
• Interleaved DMA Operation
• Fast Conversion
• A/D Process Totally Transparent to μP
• Low Cost