MICROCHIP SY89874UMG

This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622 MHz or higher) CML, LVPECL, LVDS, or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. Available divider ratios are 2, 4, 8, and 16, or straight pass-through. In a typical 622 MHz clock system this would provide availability of 311 MHz, 155 MHz, 77 MHz, or 38 MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications. The /RESET input asynchronously resets the divider. In the pass-through function (divide by 1) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /IN).

• Integrated Programmable Clock Divider and 1:2 Fanout Buffer
• Guaranteed AC Performance over Temperature and Voltage: - >2.5 GHz fMAX - <250 ps tr/tf - <15 ps Within-Device Skew
• Low Jitter Design: - <10 psₚ₋ₚ Total Jitter - <1 psRMS Cycle-to-Cycle Jitter
• Unique Input Termination and VT Pin for DC-Coupled and AC-Coupled Inputs; CML, PECL, LVDS, and HSTL
• TTL/CMOS Inputs for Select and Reset
• 100KEP-Compatible LVPECL Outputs
• Parallel Programming Capability
• Programmable Divider Ratios of 1, 2, 4, 8, and 16
• Low-Voltage Operation: 2.5V or 3.3V
• Output Disable Function
• -40℃ to +85℃ Temperature Range
• Available in 16-Pin (3 mmx3 mm) QFN Package

• SONET/SDH Line Cards
• Transponders
• High-End Multiprocessor Sensors