MICROCHIP SY89872UMG

This 2.5V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. The SY89872U includes two output banks. Bank A is an exact copy of the input clock (pass-through) with matched propagation delay to Bank B, the divided output bank. Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications. The /RESET input asynchronously resets the divider outputs (Bank B). In the pass-through function (Bank A) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /IN).

• Guaranteed AC performance over temperature and voltage:

  • 2GHz fMAX

  • <750ps tPD (matched delay between banks)
  • 15ps within-device skew <200ps rise/fall time
• Low jitter design: 265fs RMS phase jitter
• Unique input termination and VT pin for DC-coupled and AC-coupled inputs: any differential inputs (LVPECL, VDS, CML, HSTL)
• Precision differential LVDS outputs
• Matched delay: all outputs have matched delay, independent of divider setting
• TTL/CMOS inputs for select and reset/disable
• Two output banks (matched delay)
  • Bank A: Buffered copy of input clock (undivided)
  • Bank B: Divided output (÷2, ÷4, ÷8, ÷16), two copies
• 2.5V power supply
• Wide operating temperature range: -40°C to +85°C
• Available in 16-pin (3mm×3mm) QFN package

• OC-3 to OC-192 SONET/SDH applications
• Transponders
• Oscillators
• SONET/SDH line cards