Infineon CY9AF112MPMC-G-MJE1

The CY9A110A/CY9A110 Series are highly integrated 32-bit microcontrollers that target for high-performance and cost-sensitive embedded control applications. The CY9A110A Series are based on the Arm Cortex-M3 Processor and on-chip Flash memory and SRAM, and peripheral functions, including Motor Control Timers, ADCs, Communication Interfaces (UART, CSIO, I2C, LIN).

• 32-bit Arm Cortex-M3 Core
  • Processor version: r2p1
  • Up to 40 MHz Frequency Operation
  • Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels
• On-chip Memories
  • [Flash memory]
    • Up to 512 Kbyte
    • Read cycle: 0 wait-cycle
    • Security function for code protection
  • [SRAM]
    • This Series contain a total of up to 32 Kbyte on-chip SRAM. On-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is connected to I-code bus and Dcode bus of Cortex-M3 core. SRAM1 is connected to System bus.
    • SRAM0: Up to 16 Kbytes SRAM1: Up to 16 Kbytes
• Multi-function Serial Interface (Max 8 channels)
  • 4 channels with 16 steps × 9bit FIFO (ch.4 - ch.7), 4 channels without FIFO (ch.0 - ch3)
  • Operation mode is selectable from the followings for each channel: UART, CSIO, LIN, I2C
  • [UART]
    • Full duplex double buffer
    • Selection with or without parity supported
    • Built-in dedicated baud rate generator
    • External clock available as a serial clock
    • Hardware Flow control: Automatically control the transmission by CTS/RTS (only ch.4)
    • Various error detection functions available (parity errors, framing errors, and overrun errors)
  • [CSIO]
    • Full duplex double buffer
    • Built-in dedicated baud rate generator
    • Overrun error detection function available
  • [LIN]
    • LIN protocol Rev.2.1 supported
    • Full duplex double buffer
    • Master/Slave mode supported
    • LIN break field generation (can be changed 13 - 16bit length)
    • LIN break delimiter generation (can be changed 1 - 4bit length)
    • Various error detection functions available (parity errors, framing errors, and overrun errors)
  • [I2C]
    • Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported
• External Bus Interface
  • Supports SRAM, NOR Flash device
  • Up to 8 chip selects
  • 8-/16-bit Data width
  • Up to 25-bit Address bit
  • Maximum area size: Up to 256 Mbytes
  • Supports Address/Data multiplex
  • Supports external RDY function
• DMA Controller (8 channels)
  • The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process simultaneously.
  • 8 independently configured and operated channels
  • Transfer can be started by software or request from the builtin peripherals
  • Transfer address area: 32bit (4 Gbytes)
  • Transfer mode: Block transfer/Burst transfer/Demand transfer
  • Transfer data type: byte/half-word/word
  • Transfer block count: 1 to 16
  • Number of transfers: 1 to 65536
• A/D Converter (Max 16 channels)
  • [12-bit A/D Converter]
    • Successive Approximation type
    • Built-in 3units
    • Conversion time: 1.0 μs@5 V
    • Priority conversion available (priority at 2levels)
    • Scanning conversion mode
• Base Timer (Max 8 channels)
  • Operation mode is selectable from the followings for each channel: 16-bit PWM timer, 16-bit PPG timer, 16-/32-bit reload timer, 16-/32-bit PWC timer
• Multi-function Timer (Max 2 units)
  • The Multi-function timer is composed of the following blocks: 16-bit free-run timer × 3 ch/unit, Input capture × 4 ch/unit, Output compare × 6 ch/unit, A/D activation compare × 3 ch/unit, Waveform generator × 3 ch/unit, 16-bit PPG timer × 3 ch/unit
  • The following function can be used to achieve the motor control: PWM signal output function, DC chopper waveform output function, Dead timer function, Input capture function, A/D converter activate function
• Quadrature Position/Revolution Counter (QPRC)
  • The Quadrature Position/Revolution Counter (QPRC) is used to measure the position of the position encoder. Moreover, it is possible to use up/down counter.
  • The detection edge of the three external event input pins AIN, BIN and ZIN is configurable.
  • 16-bit position counter
  • 16-bit revolution counter
  • Two 16-bit compare registers
• Dual Timer (32-/16-bit Down Counter)
  • The Dual Timer consists of two programmable 32-/16-bit down counters.
  • Operation mode is selectable from the followings for each timer channel: Free-running, Periodic (=Reload), One-shot
• Watch Counter
  • The Watch counter is used for wake up from Low-Power Consumption mode.
  • Interval timer: up to 64 s(Max)
  • Sub Clock: 32.768 kHz
• Watch dog Timer (2 channels)
  • A watchdog timer can generate interrupts or a reset when a time-out value is reached.
  • This series consists of two different watchdogs, a "Hardware" watchdog and a "Software" watchdog.
  • The "Hardware" watchdog timer is clocked by the built-in lowspeed CR oscillator. Therefore, the "Hardware" watchdog is active in any low-power consumption modes except STOP modes.