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AMD/XILINX XCF02SVOG20C

Produttore
Cod. Prod.
XCF02SVOG20C
Cod. LCSC
C569040
Imballo
TSSOP-20
Numero Cliente
Attr. chiave
Platform Flash In-System Programmable Configuration PROMs
Scheda TecnicaAMD/XILINX XCF02SVOG20C
Conformità RoHS1 documenti disponibili
Disponibile: 151
151 Pronta consegna
Minimo: 1Multiplo: 1Unità di vendita: Piece
Aggiungi alla Lista BOM
QtàPr. unit.Importo totale
1+$ 41.6969$ 41.70
30+$ 35.6509$ 1069.53
Package Standard74/Full Tube
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Specifiche del Prodotto

Tutto

Descrizione

Traduzione AI

Available in 1 to 32 Mb densities, these PROMs provide an easy-to-use, cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams. The Platform Flash PROM series includes both the 3.3V XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS version includes 4 Mb, 2 Mb, and 1 Mb PROMs that support Master Serial and Slave Serial FPGA configuration modes. The XCFxxP version includes 32 Mb, 16 Mb, and 8 Mb PROMs that support Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP FPGA configuration modes. When driven from a stable, external clock, the PROMs can output data at rates up to 33 MHz. The XCFxxP version of the Platform Flash PROM also supports Master SelectMAP and Slave SelectMAP (or Slave Parallel) FPGA configuration modes. The XCFxxP version of the Platform Flash PROM provides additional advanced features. A built-in data decompressor supports utilizing compressed PROM files, and design revisioning allows multiple design revisions to be stored on a single PROM or stored across several PROMs. Multiple Platform Flash PROM devices can be cascaded to support the larger configuration files required when targeting larger FPGA devices or targeting multiple FPGAs daisy chained together.

Caratteristiche

Traduzione AI
  • In-System Programmable PROMs for Configuration of Xilinx FPGAs
  • Low-Power Advanced CMOS NOR Flash Process
  • Endurance of 20,000 Program/Erase Cycles
  • Operation over Full Industrial Temperature Range (-40℃ to +85℃)
  • IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing
  • JTAG Command Initiation of Standard FPGA Configuration
  • Cascadable for Storing Longer or Multiple Bitstreams
  • Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ)
  • I/O Pins Compatible with Voltage Levels Ranging From 1.8V to 3.3V
  • Design Support Using the Xilinx ISE Alliance and Foundation Software Packages
  • 3.3V Supply Voltage
  • Serial FPGA Configuration Interface
  • Available in Small-Footprint VO20 and VOG20 Packages
  • 1.8V Supply Voltage
  • Serial or Parallel FPGA Configuration Interface
  • Available in Small-Footprint VOG48, FS48, and FSG48 Packages
  • Design Revision Technology Enables Storing and Accessing Multiple Design Revisions for Configuration
  • Built-In Data Decompressor Compatible with Xilinx Advanced Compression Technology