TI CD74FCT16373TSM

These devices are 16-bit transparent latches designed with three-state outputs for bus-oriented applications. The output enable and latch enable controls can be configured as two 8-bit latches or one 16-bit latch. When Latch Enable (LE) is HIGH, the flip-flops are transparent to data. When LE is LOW, data meeting the setup time is latched. When OE is HIGH, the bus outputs are in a high-impedance state. The CD74FCT16373T output buffers feature a power-off disable function, allowing boards to be "hot-plugged" when used as backplane drivers. The CD74FCT162373T features ±24mA balanced output drivers. The outputs are designed with current-limiting resistors to control output edge rates, thereby reducing ground bounce and undershoot. For most interface applications, this eliminates the need for external termination resistors. The CD74FCT162H373T features a "bus-hold" function that retains the last state of the input when the input becomes high-impedance, preventing inputs from "floating" and eliminating the need for pull-up and pull-down resistors.

• Advanced 0.6-micron CMOS technology — high-speed, low-power devices with high current drive capability
• VCC = 5V ± 10%; all inputs with hysteresis
• CD74FCT16373T: high output drive, IOH = -32mA, IOL = 64mA; power-off disable output enables "hot insertion"; typical VOLP (output ground bounce) < 1.0V at VCC = 5V, TA = 25°C
• CD74FCT162373T: balanced output drivers at ±24mA; reduced system switching noise; typical VOLP (output ground bounce) < 0.6V at VCC = 5V, TA = 25°C
• CD74FCT162H373T: bus-hold feature retains last valid bus state during three-state; no external pull-up resistors required

• Bus-oriented applications