TI SN74LS221N

The '221 and 'LS221 devices are dual multivibrators with performance characteristics virtually identical to those of the '121 devices. Each multivibrator features a negative-transition triggered input and a positive-transition triggered input, either of which can be used as an inhibit input. Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with transition at rates as slow as 1 V/s providing the circuit with excellent noise immunity, typically of 1.2 V. A high immunity to VCC noise, typically of 1.5 V, also is provided by internal latching circuitry. Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration relative to the output pulse. Output pulse length can be varied from 35 ns to the maximum by choosing appropriate timing components. With Rext = 2 kΩ and Cext = 0, an output pulse typically of 30 ns is achieved that can be used as a dc-triggered reset signal. Output rise and falltimes are TTL compatible and independent of pulse length. Pulse-width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability is limited only by the accuracy of external timing components. Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing capacitance (10 pF to 10 μF) and more than one decade of timing resistance (2 kΩ to 30 kΩ for the SN54221, ≥ 1 kΩ to 40 kΩ for the SN74221, 2 kΩ to 70 kΩ for the SN54LS221, and ≥ 1 kΩ to 100 kΩ for the SN74LS221). Throughout these ranges, pulse width is defined by the relationship: tW(out)=CextRext ln2≈0.7 CextRext. In circuits where pulse cutoff is not critical, timing capacitance up to 1000 μF and timing resistance as low as 1.4 KΩ can be used. Also, the range of jitter-free output pulse widths is extended if VCC is held to 5 V and free-air temperature is 25 °C. Duty cycles as high as 90% are achieved when using maximum recommended RT. Higher duty cycles are available if a certain amount of pulse-width jitter is allowed. The variance in output pulse width from device to device typically is less than ±0.5% for given external timing components. Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123 so that the '221 or 'LS221 devices can be substituted for those products in systems not using the retrigger by merely changing the value of Rext and/or Cext however, the polarity of the capacitor must be changed.

• Dual high-stability monostable multivibrators; electrical and switching characteristics of SN54221 and SN74221 are nearly identical to those of the SN54121/SN74121 monostable multivibrators
• Pin-compatible with SN54123, SN74123, SN54LS123, and SN74LS123; can replace these devices in systems that do not use retriggering with only external timing component value changes required; observe capacitor polarity when replacing capacitors
• Each multivibrator features one negative-transition trigger input and one positive-transition trigger input; either input can be used as an inhibit input
• Output pulse can be terminated via overriding clear
• Pulse triggering occurs at a specific voltage level, independent of input transition time
• B input incorporates Schmitt-trigger input circuitry for jitter-free triggering from inputs with transition rates as slow as 1 V/s; typical noise immunity of 1.2 V
• Internal latching circuitry provides typical supply-voltage noise immunity of 1.5 V
• Output state after triggering is independent of subsequent transitions on A and B inputs; output pulse width is determined by external timing components and can be terminated early via overriding clear
• Input pulse duration can be of any length relative to the output pulse; output pulse width is adjustable from 35 ns to the maximum value by selection of appropriate external timing components
• With Rext = 2 kΩ and Cext = 0, a typical output pulse width of 30 ns is obtained, usable as a DC-triggered reset signal
• Output rise and fall times are TTL-compatible and independent of pulse duration
• Internal compensation ensures stable pulse width with minimal sensitivity to supply voltage and temperature variations; in most applications, pulse stability is limited only by the accuracy of external timing components
• Jitter-free operation is maintained over the full temperature and supply voltage ranges with timing capacitances from 10 pF to 10 μF and corresponding timing resistance ranges: SN54221: 2 kΩ–30 kΩ, SN74221: 2 kΩ–40 kΩ, SN54LS221: 2 kΩ–70 kΩ, SN74LS221: 2 kΩ–100 kΩ
• Output pulse width formula: tw(out) ≈ 0.7CextRext
• Where pulse cutoff requirements are not critical, timing capacitances up to 1000 μF and timing resistances as low as 1.4 kΩ may be used; jitter-free output pulse width range can be further extended when supply voltage is maintained at 5 V and free-air temperature is 25°C
• Duty cycles up to 90% are achievable with maximum recommended timing resistance; higher duty cycles are possible with some pulse width jitter
• Output pulse width variation between devices with identical external timing components is typically less than ±0.5%
• A input, B input, and clear pin equivalent resistances have corresponding nominal values; output characteristics conform to standard specifications
• Absolute maximum ratings: supply voltage up to 7 V; input voltage up to 7 V for SN54LS221, up to 5.5 V for 221; storage temperature range −65°C to 150°C