onsemi MC10EP195FA

The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay for differential NECL/PECL input transitions. The delay section consists of a programmable gate and multiplexer matrix. The chip offers digitally selectable delay increments with approximately 10 ps resolution and a net range of up to 10.2 ns. The desired delay is selected by the value of the 10 data select inputs D[9:0] and is controlled by LEN (pin 10). When LEN is LOW, transparent loading of real-time delay values via D[9:0] is enabled. A LOW-to-HIGH transition on LEN latches and holds the current value, unaffected by subsequent changes to D[10:0]. Approximate delay values for each tap count, corresponding to D0 (LSB) through D9 (MSB), are shown in Table 6 and Figure 4. Because the EP195 uses a multiplexer chain architecture, it has a fixed minimum delay of 2.2 ns. An additional pin D10 controls pins 14 and 15 (CASCADE and CASCADE), also latched by LEN, and is used to cascade multiple PDCs to extend the programmable range. The cascade logic allows full control over multiple PDCs. Switching D[0:9] from all "1"s (SETMAX LOW) to all "0"s (SETMAX HIGH) increases the delay by the minimum increment equivalent to "D0." The select input pins D[10:0] support threshold control via interconnect combinations between VEF (pin 7) and VCF (pin 8) to accommodate LVCMOS, ECL, or LVTTL level signals. For LVCMOS input levels, leave VCF and VEF open. For ECL operation, short VCF and VEF (pins 7 and 8) together. For LVTTL level operation, connect a 1.5 V supply reference to VCF and leave the VEF pin open. A 1.5 V reference for the VCF pin can be generated by placing a 2.2 kΩ resistor between VCF and VEE under a 3.3 V supply. The VBB pin is an internally generated voltage source for use by this device only. For single-ended input conditions, unused differential inputs are connected to VBB as a switching reference voltage. VBB can also re-bias AC-coupled inputs. When in use, decouple VBB and VCC with a 0.01 μF capacitor and limit current sourcing or sinking to 0.5 mA. When not in use, VBB should be left open. The 100 series includes temperature compensation. Typical maximum input clock frequency is >1.2 GHz.

• Programmable range: 0 ns to 10 ns
• Delay range: 2.2 ns to 12.2 ns
• 10 ps increments
• PECL mode operating range: VCC = 3.0 V to 3.6 V, VEE = 0 V
• NECL mode operating range: VCC = 0 V, VEE = -3.0 V to -3.6 V
• Open input default state
• Safety clamp on inputs
• EN pin logic high forces Q to logic low
• D[10:0] accepts ECL, LVCMOS, or LVTTL inputs
• VBB output reference voltage
• Available in lead-free package