onsemi MC74HC165FL1

74HC165 and 74HCT165 are high-speed silicon gate CMOS devices compliant with JEDEC standard 7A. Their pinouts are compatible with Low-power Schottky TTL (LSTTL). The 74HC165 and 74HCT165 are 8-bit parallel-load or serial-input shift registers with complementary serial outputs (Q7 and Q7 (overline)) available from the last stage. When the parallel load (PL (overline)) input is LOW, parallel data from inputs D0 to D7 is asynchronously loaded into the register. When PL (overline) is HIGH, data enters the register serially at the DS input and shifts one bit to the right on each rising clock edge (Q0 → Q1 → Q2, etc.). This feature allows expansion of parallel-to-serial converters by connecting the Q7 output to the DS input of the next stage. The clock input uses a gated OR structure that allows one input to function as an active-LOW clock enable (CE) input. The pin assignment of the CP and CE inputs is arbitrary and may be swapped for layout convenience. For predictable operation, LOW-to-HIGH transitions on CE should occur only while CP is HIGH. Prior to a LOW-to-HIGH transition on PL, at least one of CP or CE should be HIGH to prevent data shifting when PL is activated.

• Asynchronous 8-bit parallel load
• Synchronous serial input
• Complies with JEDEC standard no. 7A
• ESD protection:
  • HBM JESD22-A114E exceeds 2000 V
  • MM JESD22-A115-A exceeds 200 V
• Specified from -40 ℃ to +85 ℃ and from -40 ℃ to +125 ℃

Parallel-to-Serial Data Conversion