TI IP80C86

The Harris 80C86 high performance 16-bit CMOS CPU is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). Two modes of operation, minimum for small systems and maximum for larger applications such as multiprocessing. allow user configuration to achieve the highest performance level. Full TTL compatibility (with the exception of CLOCK) and industry standard operation allow use of existing NMOS 8086 hardware and software designs.

• Compatible with NM0S 8086
• Completely Static CMOs Design - DC to 5MHz (80C86) - DC to 8MHz (80C86 - 2)
• Low Power Operation - ICCSB: 500μA Max - ICCOP: 10mA/MHz Typ
• 1 MByte of Direct Memory Addressing Capability
• 24 Operand Addressing Modes
• Bit, Byte, Word and Block Move Operations
• 8 - Bit and 16 - Bit Signed/Unsigned Arithmetic - Binary, or Decimal - Multiply and Divide
• Wide Operating Temperature Range - C80C86: 0℃ to +70℃ - l80C86: -20℃ to +85℃ - M80C86: -55℃ to +125℃

• Minimum mode for small systems and maximum mode for large applications (e.g., multiprocessing).
• Compatible with existing NMOS 8086 hardware and software designs.
• Ultra-low power operation for power-critical applications.
• Suitable for system debugging or power-critical applications.
• Multiprocessor configuration support, allowing coprocessors in local and remote bus configurations.
• Standard non-multiplexed bus architecture with heavy bus buffering and relaxed bus timing requirements.
• Decodes status lines S0, S1, and S2 via the 82C88 bus controller, providing all bus control signals.