Rochester Electronics AM79C961AVI

The PCnet-ISA II controller is a highly integrated single-chip Ethernet controller designed for the PC-AT Industry Standard Architecture (ISA) and Extended Industry Standard Architecture (EISA) buses. It is intended to provide flexibility and compatibility for a wide range of existing PC applications. This VLSI device is designed to reduce component count and cost while meeting the demands of applications requiring higher system throughput. The controller is fabricated using an advanced low-power CMOS process, providing low standby current for power-sensitive applications. The PCnet-ISA II controller can be configured in three distinct architecture modes to accommodate specific PC applications. In Bus Master mode, all data transfers are performed using the integrated DMA controller, bypassing the platform DMA controller and directly addressing the full 24-bit memory space to enhance system performance and minimize component count. The controller can also be configured in Bus Slave mode, using either a shared memory or programmed I/O architecture, to support compatibility with low-end machines (such as PC/XT) that do not support bus mastering, as well as high-end machines requiring local packet buffering to accommodate increased system latency. The PCnet-ISA II controller is designed to connect directly to the ISA or EISA system bus. It incorporates an ISA Plug and Play bus interface unit, a DMA buffer management unit, 802.3 media access control functions, separate 136-byte transmit and 128-byte receive FIFOs, an IEEE 802.3-defined Attachment Unit Interface, and a twisted-pair transceiver media attachment unit. The device supports full-duplex network operation on either of its network ports. The controller is register-compatible with the LANCE (Am7990) Ethernet controller and the PCnet-ISA (Am79C960), and its DMA buffer management unit supports the LANCE descriptor software model. It also supports an external remote boot and Ethernet physical address PROM and EEPROM. This advanced Ethernet controller features built-in automatic selection between the AUI port and the twisted-pair transceiver, with only one interface active at any given time. The separate 136-byte transmit and 128-byte receive FIFOs optimize system overhead by providing sufficient latency during packet transmission and reception, and minimizing intervention during normal network error recovery. The integrated Manchester encoder/decoder eliminates the need for an external serial interface adapter at the node system. If support for an external encoding/decoding scheme is required, the embedded general-purpose serial interface allows direct access to the MAC. In addition, the device provides programmable on-chip LED drivers for indicating transmit, receive, collision, receive polarity, link integrity and activity status, or long frame status. The PCnet-ISA II controller also provides an external address detection interface to allow external hardware address filtering in network interconnect applications.

• Single-chip Ethernet controller for ISA and EISA buses
• IEEE 802.3/ANSI 8802-3 and Ethernet standard compliant
• Full-duplex operation on 10BASE-T
• Direct connection to ISA or EISA bus
• Pin-compatible with Am79C961 PCnet-ISA+ jumperless single-chip Ethernet controller
• Software-compatible with AMD Am7990 LANCE register and descriptor architecture
• Low-power CMOS design with sleep mode for reduced power consumption in battery-powered applications
• Separate 136-byte transmit and 128-byte receive FIFOs for packet buffering and increased system latency tolerance, supporting: automatic retransmission without FIFO reload, automatic receive stripping and transmit padding (independently programmable), automatic short packet rejection, automatic collision fragment deletion
• Dynamic transmit FCS generation, programmable on a per-frame basis
• Single +5V supply
• Internal/external loopback capability
• 8K, 16K, 32K, and 64K boot PROM or Flash memory support for diskless node applications
• Microsoft Plug and Play system configuration support for jumperless design
• Staggered AT bus driving to reduce noise and ground bounce
• Integrated Magic Packet™ support for remote wake-up of green PCs
• 8 on-chip interrupts
• Look-ahead packet processing for protocol analysis before end of received frame
• 4 on-chip DMA channels
• 16 I/O address support
• 16 boot PROM address support
• Integrated AUI and 10BASE-T transceiver with 2 port selection modes: auto-select AUI or 10BASE-T, software-select AUI or 10BASE-T
• Automatic twisted-pair receive polarity detection and correction
• Bus master, programmable I/O, and shared memory architecture support for any PC application
• Edge- and level-sensitive interrupt support
• DMA buffer management unit reduces CPU intervention and increases throughput by bypassing platform DMA
• JTAG boundary scan test access port interface for board-level production testing
• Integrated Manchester encoder/decoder
• Network interface types supported: AUI for external 10BASE2, 10BASE5, 10BASE-T, or 10BASE-F MAU; internal 10BASE-T transceiver with intelligent squelch for twisted-pair media
• LANCE Generic Serial Interface support
• 132-pin PQFP and 144-pin TQFP packages
• Shared memory and PIO mode support
• PCMCIA mode support (144-TQFP version only)
• Industrial temperature range operation (-40℃ ~ +85℃) available in both packages