Infineon/CYPRESS CY8C4045PVI-DS402

PSoC 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm Cortex - M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4200DS product family, based on this platform architecture, is a combination of a microcontroller with digital programmable logic, programmable interconnect, and standard communication and timing peripherals. The PSoC 4200DS products will be fully compatible with members of the PSoC 4 platform for new applications and design needs. The programmable digital subsystem allows flexibility and in - field tuning of the design.

• 48 MHz Arm Cortex - M0 CPU with single - cycle multiply
• Up to 64 KB of flash with Read Accelerator
• Up to 8 kB of SRAM
• Up to 21 programmable GPIOs
• GPIO drive modes, strengths, and slew rates are programmable
• Four programmable logic blocks, each with 8 Macrocells and an 8 - bit data path (called universal digital blocks or UDBs)
• Programmable I/O block (PRGIO) provides the ability to perform Boolean functions in the I/O signal path
• Cypress - provided peripheral component library, user - defined state machines, and Verilog input
• Integrated development environment (IDE) provides schematic design entry and build (with analog and digital automatic routing)
• Application programming interface (API) component for all fixed - function and programmable peripherals
• Low - power Deep Sleep Mode with GPIO pin wakeup
• After schematic entry, development can be done with Arm - based industry - standard development tools
• Three independent run - time reconfigurable serial communication blocks (SCBs) with reconfigurable I2C, SPI, or UART functionality
• Four 16 - bit timer/counter pulse - width modulator (TCPWM) blocks
• Center - aligned, Edge, and Pseudo - random modes
• Comparator - based triggering of Kill signals for motor drive and other high - reliability digital logic applications